Datasheet > LC5256MB-4FN208I

LC5256MB-4FN208I

更新时间： 2024-11-21 05:23:39

品牌	Logo	应用领域
莱迪思 - LATTICE		可编程逻辑器件
页数	文件大小	规格书
92页	601K
描述
3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family

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LC5256MB-4FN208I 数据手册

ispXPLD 5000MX Family

3.3V, 2.5V and 1.8V In-System Programmable

eXpanded Programmable Logic Device XPLD™ Family

March 2006

Data Sheet

■ Expanded In-System Programmability (ispXP™)

• Instant-on capability

Features

■ Flexible Multi-Function Block (MFB)

Architecture

• Single chip convenience

• In-System Programmable via IEEE 1532

Interface

• Inﬁnitely reconﬁgurable via IEEE 1532 or

sysCONFIG™ microprocessor interface

• Design security

• SuperWIDE™ logic (up to 136 inputs)

• Arithmetic capability

• Single- or Dual-port SRAM

• FIFO

• Ternary CAM

■ High Speed Operation

■ sysCLOCK™ PLL Timing Control

• Multiply and divide between 1 and 32

• Clock shifting capability

• 4.0ns pin-to-pin delays, 300MHz f

• Deterministic timing

MAX

■ Low Power Consumption

• External feedback capability

• Typical static power: 20 to 50mA (1.8V),

30 to 60mA (2.5/3.3V)

■ sysIO™ Interfaces

• LVCMOS 1.8, 2.5, 3.3V

– Programmable impedance

– Hot-socketing

• 1.8V core for low dynamic power

■ Easy System Integration

• 3.3V (5000MV), 2.5V (5000MB) and 1.8V

(5000MC) power supply operation

• 5V tolerant I/O for LVCMOS 3.3 and LVTTL

interfaces

– Flexible bus-maintenance (Pull-up, pull-

down, bus-keeper, or none)

– Open drain operation

• SSTL 2, 3 (I & II)

• HSTL (I, III, IV)

• PCI 3.3

• GTL+

• LVDS

• LVPECL

• IEEE 1149.1 interface for boundary scan testing

• sysIO quick conﬁguration

• Density migration

• Multiple density and package options

• PQFP and ﬁne pitch BGA packaging

• Lead-free package options

• LVTTL

Table 1. ispXPLD 5000MX Family Selection Guide

ispXPLD 5256MX ispXPLD 5512MX ispXPLD 5768MX ispXPLD 51024MX

Macrocells

256

512

768

1,024

Multi-Function Blocks

Maximum RAM Bits

Maximum CAM Bits

sysCLOCK PLLs

128K

48K

256K

384K

144K

512K

192K

96K

(Propagation Delay)

4.0ns

2.2ns

2.8ns

300MHz

75K

4.5ns

2.8ns

3.0ns

275MHz

150K

5.0ns

2.8ns

3.2ns

250MHz

225K

193/317

5.2ns

3.0ns

3.7ns

250MHz

300K

317/381

t (Register Set-up Time)

(Register Clock to Out Time)

(Maximum Operating Frequency)

MAX

System Gates

I/Os

141

149/193/253

Packages

208 PQFP

256 fpBGA

484 fpBGA

256 fpBGA

484 fpBGA

672 fpBGA

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

5kmx_12.2

12 3 4 5 6 7...92

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与LC5256MB-4FN208I相关器件

型号	品牌	获取价格	描述	数据表
LC5256MB-4FN256C	LATTICE	获取价格	3.3V, 2.5V and 1.8V In-System Programmable eX
LC5256MB-4FN256I	LATTICE	获取价格	3.3V, 2.5V and 1.8V In-System Programmable eX
LC5256MB-4FN484C	LATTICE	获取价格	3.3V, 2.5V and 1.8V In-System Programmable eX
LC5256MB-4FN484I	LATTICE	获取价格	3.3V, 2.5V and 1.8V In-System Programmable eX
LC5256MB-4FN672C	LATTICE	获取价格	3.3V, 2.5V and 1.8V In-System Programmable eX
LC5256MB-4FN672I	LATTICE	获取价格	3.3V, 2.5V and 1.8V In-System Programmable eX
LC5256MB-4Q208C	LATTICE	获取价格	3.3V, 2.5V and 1.8V In-System Programmable eX
LC5256MB-4Q208I	LATTICE	获取价格	3.3V, 2.5V and 1.8V In-System Programmable eX
LC5256MB-4Q256C	LATTICE	获取价格	3.3V, 2.5V and 1.8V In-System Programmable eX
LC5256MB-4Q256I	LATTICE	获取价格	3.3V, 2.5V and 1.8V In-System Programmable eX

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