LAN9352
2-Port 10/100 Managed Ethernet Switch with
8/16-Bit Non-PCI CPU Interface
• Ports
Highlights
- 2 internal 10/100 PHYs with HP Auto-MDIX
support
• High performance 2-port switch with VLAN, QoS
packet prioritization, rate limiting, IGMP monitoring
and management functions
• Interfaces to most 8/16-bit embedded controllers
and 32-bit embedded controllers with an 8/16-bit
bus
• Integrated Ethernet PHYs with HP Auto-MDIX
• Compliant with Energy Efficient Ethernet 802.3az
• Wake on LAN (WoL) support
• Integrated IEEE 1588v2 hardware time stamp unit
• Cable diagnostic support
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Fully compliant with IEEE 802.3 standards
10BASE-T and 100BASE-TX support
100BASE-FX support via external fiber transceiver
Full and half duplex support, full duplex flow control
Backpressure (forced collision) half duplex flow control
Automatic flow control based on programmable levels
Automatic 32-bit CRC generation and checking
Programmable interframe gap, flow control pause value
Auto-negotiation, polarity correction & MDI/MDI-X
• 8/16-Bit Host Bus Interface
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Indexed register or multiplexed bus
SPI / Quad SPI support
• 1.8V to 3.3V variable voltage I/O
• Integrated 1.2V regulator for single 3.3V operation
• IEEE 1588v2 hardware time stamp unit
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Global 64-bit tunable clock
Boundary clock: timeTransmitter / timeReceiver, one-
step / two-step, end-to-end / peer-to-peer delay
Transparent Clock with Ordinary Clock:
timeTransmitter / timeReceiver, one-step / two-step,
end-to-end / peer-to-peer delay
Fully programmable timestamp on TX or RX,
timestamp on GPIO
64-bit timer comparator event generation (GPIO or IRQ)
Target Applications
• Cable, satellite, and IP set-top boxes
• Digital televisions & video recorders
• VoIP/Video phone systems, home gateways
• Test/Measurement equipment, industrial automation
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Key Benefits
• Comprehensive power management features
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3 power-down levels
• Ethernet Switch Fabric
Wake on link status change (energy detect)
Magic packet wakeup, Wake on LAN (WoL), wake on
broadcast, wake on perfect DA
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32K buffer RAM, 512 entry forwarding table
Port based IEEE 802.1Q VLAN support (16 groups)
-Programmable IEEE 802.1Q tag insertion/removal
IEEE 802.1D spanning tree protocol support
4 separate transmit queues available per port
Fixed or weighted egress priority servicing
QoS/CoS Packet prioritization
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Wakeup indicator event signal
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• Power and I/O
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Integrated power-on reset circuit
Latch-up performance exceeds 150mA
per EIA/JESD78, Class II
JEDEC Class 3A ESD performance
Single 3.3V power supply
(integrated 1.2V regulator)
-Input priority determined by VLAN tag, DA lookup,
TOS, DIFFSERV or port default value
-Programmable Traffic Class map based on input pri-
ority on per port basis
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-Remapping of 802.1Q priority field on per port basis
-Programmable rate limiting at the ingress with color-
ing and random early discard, per port / priority
-Programmable rate limiting at the egress with leaky
bucket algorithm, per port / priority
• Additional Features
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Multifunction GPIOs
Ability to use low cost 25MHz crystal for reduced BOM
• Packaging
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Pb-free RoHS compliant 72-pin QFN or 80-pin TQFP-
EP
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IGMP v1/v2/v3 monitoring for Multicast packet filtering
Programmable broadcast storm protection with global %
control and enable per port
• Available in commercial and industrial temp. ranges
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Programmable buffer usage limits
Dynamic queues on internal memory
Programmable filter by MAC address
• Switch Management
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Port mirroring/monitoring/sniffing: ingress and/or egress
traffic on any port or port pair
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Fully compliant statistics (MIB) gathering counters
2023 Microchip Technology Inc. and its subsidiaries
DS00001923B-page 1
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