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LAN9250 PDF预览

LAN9250

更新时间: 2023-12-06 20:11:31
品牌 Logo 应用领域
美国微芯 - MICROCHIP 局域网局域网(LAN)标准
页数 文件大小 规格书
419页 3933K
描述
The LAN9250 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded appli

LAN9250 数据手册

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LAN9250  
10/100 Industrial Ethernet Controller & PHY  
• 8/16-Bit Host Bus Interface  
Highlights  
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Indexed register or multiplexed bus  
16Kbyte FIFO with flexible TX/RX allocation  
SPI / Quad SPI support  
• 16-bit 10/100 industrial Ethernet controller & PHY  
• Interfaces to most 8/16-bit embedded controllers  
and 32-bit embedded controllers with an 8/16-bit  
bus  
• Integrated Ethernet PHY with HP Auto-MDIX  
• Integrated Ethernet MAC  
• Compliant with Energy Efficient Ethernet 802.3az  
• Wake on LAN (WoL) support  
• Integrated IEEE 1588v2 hardware time stamp unit  
• Cable diagnostic support  
• IEEE 1588v2 hardware time stamp unit  
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Global 64-bit tunable clock  
Ordinary clock: timeTransmitter / timeReceiver, one-  
step / two-step, end-to-end / peer-to-peer delay  
Fully programmable timestamp on TX or RX,  
timestamp on GPIO  
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64-bit timer comparator event generation (GPIO or IRQ)  
• Comprehensive power management features  
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3 power-down levels  
• 1.8V to 3.3V variable voltage I/O  
• Integrated 1.2V regulator for single 3.3V operation  
• Low pin count and small body size package  
Wake on link status change (energy detect)  
Magic packet wakeup, Wake on LAN (WoL), wake on  
broadcast, wake on perfect DA  
Wakeup indicator event signal  
Link status change  
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Target Applications  
• Power and I/O  
• Cable, satellite, and IP set-top boxes  
• Digital televisions & video recorders  
• VoIP/Video phone systems  
• Home gateways  
Test/Measurement equipment  
• Industrial automation systems  
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Integrated power-on reset circuit  
Latch-up performance exceeds 150mA  
per EIA/JESD78, Class II  
JEDEC Class 3A ESD performance  
Single 3.3V power supply  
(integrated 1.2V regulator)  
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• Additional Features  
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Multifunction GPIOs  
General purpose timer  
Optional EEPROM interface  
Ability to use low cost 25MHz crystal for reduced BOM  
Key Benefits  
• Single-chip Ethernet controller  
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Fully compliant with IEEE 802.3/802.3u standards  
Integrated Ethernet MAC and PHY  
10BASE-T and 100BASE-TX support  
100BASE-FX support for external fiber transceiver  
Automatic polarity detection and correction  
(HP Auto-MDIX)  
• Packaging  
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Pb-free RoHS compliant 64-pin QFN or 64-pin TQFP-  
EP  
• Available in commercial, industrial, and extended  
industrial* temp. ranges  
*Extended temp. (105ºC) is supported only in the 64-QFN with an  
external voltage regulator (internal regulator must be disabled) and  
2.5V (typ) Ethernet magnetics.  
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Full- and Half-duplex support  
Full-duplex flow control  
Backpressure for half-duplex flow control  
Preamble generation and removal  
Automatic 32-bit CRC generation and checking  
Automatic payload padding and pad removal  
Loop-back modes  
• Eliminates dropped packets  
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Internal buffer memory can store over 200 packets  
Automatic PAUSE and back-pressure flow control  
• Flexible address filtering modes  
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One 48-bit perfect address  
64 hash-filtered multicast addresses  
Pass all multicast  
Promiscuous mode  
Inverse filtering  
Pass all incoming with status report  
Disable reception of broadcast packets  
2023 Microchip Technology Inc. and its subsidiaries  
DS00001913B-page 1  

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