5秒后页面跳转
捷配首页

Datasheet > LAN9250TI/ML
LAN9250TI/ML PDF预览

LAN9250TI/ML

更新时间： 2024-01-03 14:00:35
品牌 Logo 应用领域
美国微芯 - MICROCHIP 局域网外围集成电路
页数 文件大小 规格书
421页 2456K
描述
IC,LAN NODE CONTROLLER,LLCC,64PIN

阅读下载

中文翻译

获取价格

LAN9250TI/ML 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：QCCN, LCC64,.35SQ,20Reach Compliance Code：compliant
HTS代码：8542.31.00.01Factory Lead Time：16 weeks
风险等级：5.22JESD-30 代码：S-PQCC-N64
JESD-609代码：e3端子数量：64
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：QCCN
封装等效代码：LCC64,.35SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER电源：1.2,3.3 V
认证状态：Not Qualified子类别：Serial IO/Communication Controllers
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn) - annealed端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
uPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, LANBase Number Matches：1

LAN9250TI/ML 数据手册

 浏览型号LAN9250TI/ML的Datasheet PDF文件第2页浏览型号LAN9250TI/ML的Datasheet PDF文件第3页浏览型号LAN9250TI/ML的Datasheet PDF文件第4页浏览型号LAN9250TI/ML的Datasheet PDF文件第5页浏览型号LAN9250TI/ML的Datasheet PDF文件第6页浏览型号LAN9250TI/ML的Datasheet PDF文件第7页 
LAN9250  
10/100 Industrial Ethernet Controller & PHY  
• 8/16-Bit Host Bus Interface  
Highlights  
-
-
-
Indexed register or multiplexed bus  
16Kbyte FIFO with flexible TX/RX allocation  
SPI / Quad SPI support  
• 16-bit 10/100 industrial Ethernet controller & PHY  
• Interfaces to most 8/16-bit embedded controllers  
and 32-bit embedded controllers with an 8/16-bit  
bus  
• Integrated Ethernet PHY with HP Auto-MDIX  
• Integrated Ethernet MAC  
• Compliant with Energy Efficient Ethernet 802.3az  
• Wake on LAN (WoL) support  
• Integrated IEEE 1588v2 hardware time stamp unit  
• Cable diagnostic support  
• IEEE 1588v2 hardware time stamp unit  
-
Global 64-bit tunable clock  
-
Ordinary clock: master / slave, one-step / two-step, end-  
to-end / peer-to-peer delay  
-
-
Fully programmable timestamp on TX or RX,  
timestamp on GPIO  
64-bit timer comparator event generation (GPIO or IRQ)  
• Comprehensive power management features  
-
-
-
3 power-down levels  
• 1.8V to 3.3V variable voltage I/O  
• Integrated 1.2V regulator for single 3.3V operation  
• Low pin count and small body size package  
Wake on link status change (energy detect)  
Magic packet wakeup, Wake on LAN (WoL), wake on  
broadcast, wake on perfect DA  
Wakeup indicator event signal  
Link status change  
-
-
Target Applications  
• Power and I/O  
• Cable, satellite, and IP set-top boxes  
• Digital televisions & video recorders  
• VoIP/Video phone systems  
• Home gateways  
• Test/Measurement equipment  
• Industrial automation systems  
-
-
Integrated power-on reset circuit  
Latch-up performance exceeds 150mA  
per EIA/JESD78, Class II  
JEDEC Class 3A ESD performance  
Single 3.3V power supply  
(integrated 1.2V regulator)  
-
-
• Additional Features  
-
-
-
-
Multifunction GPIOs  
General purpose timer  
Optional EEPROM interface  
Ability to use low cost 25MHz crystal for reduced BOM  
Key Benefits  
• Single-chip Ethernet controller  
-
-
-
-
-
Fully compliant with IEEE 802.3/802.3u standards  
Integrated Ethernet MAC and PHY  
10BASE-T and 100BASE-TX support  
100BASE-FX support for external fiber transceiver  
Automatic polarity detection and correction  
(HP Auto-MDIX)  
• Packaging  
-
Pb-free RoHS compliant 64-pin QFN or 64-pin TQFP-  
EP  
• Available in commercial, industrial, and extended  
industrial* temp. ranges  
*Extended temp. (105ºC) is supported only in the 64-QFN with an  
external voltage regulator (internal regulator must be disabled) and  
2.5V (typ) Ethernet magnetics.  
-
-
-
-
-
-
-
Full- and Half-duplex support  
Full-duplex flow control  
Backpressure for half-duplex flow control  
Preamble generation and removal  
Automatic 32-bit CRC generation and checking  
Automatic payload padding and pad removal  
Loop-back modes  
• Eliminates dropped packets  
-
Internal buffer memory can store over 200 packets  
-
Automatic PAUSE and back-pressure flow control  
• Flexible address filtering modes  
-
-
-
-
-
-
-
One 48-bit perfect address  
64 hash-filtered multicast addresses  
Pass all multicast  
Promiscuous mode  
Inverse filtering  
Pass all incoming with status report  
Disable reception of broadcast packets  
2015 Microchip Technology Inc.  
DS00001913A-page 1  
1234567...421

中文翻译

下载PDF

与LAN9250TI/ML相关器件

型号 品牌 描述 获取价格 数据表
LAN9250TV/ML MICROCHIP IC,LAN NODE CONTROLLER,LLCC,64PIN

获取价格
LAN9250V/ML MICROCHIP IC,LAN NODE CONTROLLER,LLCC,64PIN

获取价格
LAN9252/PT MICROCHIP LAN9252/PT

获取价格
LAN9252I/PT MICROCHIP LAN9252I/PT

获取价格
LAN9252T/PT MICROCHIP LAN9252T/PT

获取价格
LAN9255 MICROCHIP 2/3-Port EtherCAT® Device Controller with In

获取价格

与LAN9250TI/ML相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证