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LAN9215I-MT-E3 PDF预览

LAN9215I-MT-E3

更新时间: 2024-01-21 21:38:28
品牌 Logo 应用领域
美国微芯 - MICROCHIP 局域网
页数 文件大小 规格书
138页 1667K
描述
LAN9215I-MT-E3

LAN9215I-MT-E3 技术参数

生命周期:ObsoleteReach Compliance Code:unknown
风险等级:5.06Base Number Matches:1

LAN9215I-MT-E3 数据手册

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LAN9215i  
Highly Efficient Single-Chip  
10/100 Ethernet Controller  
with HP Auto-MDIX and  
Industrial Temperature  
Support  
Datasheet  
PRODUCT FEATURES  
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Single chip Ethernet controller  
Highlights  
Fully compliant with IEEE 802.3/802.3u standards  
Integrated Ethernet MAC and PHY  
10BASE-T and 100BASE-TX support  
Full- and Half-duplex support  
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Optimized for medium performance applications  
Efficient architecture with low CPU overhead  
Easily interfaces to most 16-bit embedded CPU’s  
Integrated PHY with HP Auto-MDIX  
Full-duplex flow control  
Backpressure for half-duplex flow control  
Preamble generation and removal  
Automatic 32-bit CRC generation and checking  
Automatic payload padding and pad removal  
Loop-back modes  
Supports audio & video streaming over Ethernet:  
multiple standard-definition (SD) MPEG2 streams  
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Compatible with other members of LAN9218 family  
Target Applications  
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Flexible address filtering modes  
One 48-bit perfect address  
64 hash-filtered multicast addresses  
Pass all multicast  
Promiscuous mode  
Inverse filtering  
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Basic cable, satellite, and IP set-top boxes  
Digital video recorders  
Video-over IP solutions, IP PBX & video phones  
Wireless routers & access points  
Audio distribution systems  
Pass all incoming with status report  
Disable reception of broadcast packets  
Printers, kiosks, security systems  
General embedded applications  
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Integrated 10/100 Ethernet PHY  
Supports HP Auto-MDIX  
Auto-negotiation  
Supports energy-detect power down  
Key Benefits  
High-Performance host bus interface  
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Non-PCI Ethernet controller for medium performance  
applications  
Simple, SRAM-like interface  
16-bit data bus  
16Kbyte FIFO with flexible TX/RX allocation  
One configurable host interrupt  
16-bit interface  
Burst-mode read support  
External MII Interface  
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Miscellaneous features  
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Eliminates dropped packets  
Low-profile 100-pin TQFP, lead-free RoHS Compliant  
package  
Integrated 1.8V regulator  
General Purpose Timer  
Optional EEPROM interface  
Support for 3 status LEDs multiplexed with  
Programmable GPIO signals  
Internal buffer memory can store over 200 packets  
Automatic PAUSE and back-pressure flow control  
Minimizes CPU overhead  
Supports Slave-DMA  
Interrupt Pin with Programmable Hold-off timer  
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Reduces system cost and increases design flexibility  
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Single 3.3V Power Supply with 5V tolerant I/O  
SRAM-like interface easily interfaces to most  
embedded CPU’s or SoC’s  
-40°C to +85°C Industrial Temperature Support  
* Third-party brands and names are the property of their respective  
owners.  
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Reduced Power Modes  
Numerous power management modes  
Wake on LAN*  
Magic packet wakeup*  
Wakeup indicator event signal  
Link Status Change  
SMSC LAN9215i  
DATASHEET  
Revision 1.93 (12-12-07)  

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