LAN9215
The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive FIFO which is sep-
arate from the TX and RX FIFOs. The FIFOs within the MAC are not directly accessible from the host interface. The
differentiation between the TX/RX FIFO memory buffers and the MAC buffers is that when the transmit or receive pack-
ets are in the MAC buffers, the host no longer can control or access the TX or RX data. The MAC buffers (both TX and
RX) are in effect the working buffers of the Ethernet MAC logic. In the case of reception, the data must be moved first
to the RX FIFOs for the host to access the data. For TX operations, the MIL operates in store-and-forward mode and
will queue an entire frame before beginning transmission.
1.6
Receive and Transmit FIFOs
The Receive and Transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a conduit between
the host interface and the MAC through which all transmitted and received data and status information is passed. Deep
FIFOs allow a high degree of latency tolerance relative to the various transport and OS software stacks thus reducing
or minimizing overrun conditions. Like the MAC, the FIFOs have separate receive and transmit data paths. In addition,
the RX and TX FIFOs are configurable in size, allowing increased flexibility.
1.7
Interrupt Controller
The LAN9215 supports a single programmable interrupt. The programmable nature of this interrupt allows the user the
ability to optimize performance dependent upon the application requirement. Both the polarity and buffer type of the
interrupt pin are configurable for the external interrupt processing. The interrupt line can be configured as an open-drain
output to facilitate the sharing of interrupts with other devices. In addition, a programmable interrupt de-assertion interval
is provided.
1.8
GPIO Interface
A 3-bit GPIO and 2-bit GPO (Multiplexed on the EEPROM and LED Pins) interface is included in the LAN9215. It is
accessible through the host bus interface via the CSRs. The GPIO signals can function as inputs, push-pull outputs and
open drain outputs. The GPIO’s (GPO’s are not configurable) can also be configured to trigger interrupts with program-
mable polarity.
1.9
Serial EEPROM Interface
A serial EEPROM interface is included in the LAN9215. The serial EEPROM is optional and can be programmed with
the LAN9215 MAC address. The LAN9215 can optionally load the MAC address automatically after power-on reset,
hardware reset, or soft reset.
1.10 Power Management Controls
The LAN9215 supports comprehensive array of power management modes to allow use in power sensitive applications.
Wake on LAN, Link Status Change and Magic Packet detection are supported by the LAN9215. An external PME (Power
Management Event) interrupt is provided to indicate detection of a wakeup event.
1.11 General Purpose Timer
The general-purpose timer has no dedicated function within the LAN9215 and may be programmed to issue a timed
interrupt.
1.12 Host Bus Interface (SRAM Interface)
The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as an interface for the
LAN9215 Control and Status Registers (CSR’s).
The host bus interface is the primary bus for connection to the embedded host system. This interface models an asyn-
chronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface. Programmed I/O transactions are
supported.
The LAN9215 host bus interface supports 16-bit bus transfers. Internally, all data paths are 32-bits wide. The LAN9215
can be interfaced to either Big-Endian or Little-Endian processors.
2006-2017 Microchip Technology Inc.
DS00002412A-page 7
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