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LAN91C100-SD PDF预览

LAN91C100-SD

更新时间： 2023-01-02 14:44:38
品牌 Logo 应用领域
美国微芯 - MICROCHIP 局域网外围集成电路
页数 文件大小 规格书
101页 351K
描述
IC,LAN NODE CONTROLLER,QFP,208PIN

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中文翻译

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LAN91C100-SD 技术参数

是否Rohs认证： 不符合生命周期：Active
Reach Compliance Code：unknown风险等级：5.92
JESD-30 代码：S-PQFP-G208端子数量：208
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP208,1.2SQ,20封装形状：SQUARE
封装形式：FLATPACK电源：5 V
认证状态：Not Qualified子类别：Serial IO/Communication Controllers
最大压摆率：95 mA标称供电电压：5 V
表面贴装：YES温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUADuPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, LAN

LAN91C100-SD 数据手册

 浏览型号LAN91C100-SD的Datasheet PDF文件第2页浏览型号LAN91C100-SD的Datasheet PDF文件第3页浏览型号LAN91C100-SD的Datasheet PDF文件第4页浏览型号LAN91C100-SD的Datasheet PDF文件第5页浏览型号LAN91C100-SD的Datasheet PDF文件第6页浏览型号LAN91C100-SD的Datasheet PDF文件第7页 
LAN91C100  
ADVANCE INFORMATION  
FEAST™  
Fast Ethernet Controller  
FEATURES  
Dual Speed CSMA/CD Engine (10 Mbps  
and 100 Mbps)  
Built-in Transparent Arbitration for Slave  
·
·
·
·
·
Sequential Access Architecture  
Flat MMU Architecture with Symmetric  
Transmit and Receive Structures and  
Queues  
MII (Media Independent Interface)  
Compliant MAC-PHY Interface (Compliant  
with Emerging MII Standard Interface)  
MII Management Serial Interface  
Seven Wire Interface to 10 Mbps ENDEC  
(LAN83C694)  
Compliant with IEEE 802.3 100BASE-T  
Specification  
Supports 100BASE-TX, 100BASE-T4, and  
10BASE-T Physical Interfaces  
32 Bit Wide Data Path (Into Packet Buffer  
Memory)  
Support for 32 and 16 Bit Buses  
Support for 32, 16 and 8 Bit CPU Accesses  
Synchronous, Asynchronous and Burst  
DMA Interface Mode Options  
128 Kbyte External Memory  
·
·
·
·
·
·
·
EEPROM-Based Setup  
208 Pin PQFP and TQFP Package  
·
·
·
GENERAL DESCRIPTION  
a high-speed dynamically allocates buffer memory in an  
The LAN91C100 FEAST is  
network controller designed to facilitate the  
implementation of Fast Ethernet adapters and  
connectivity products. It contains a dual speed  
CSMA/CD engine that implements the MAC  
portion of the CSMA/CD protocol at 10 and 100  
Mbps and couples it with a lean and fast data  
and control path system architecture to ensure  
data movement with no bottlenecks at 100  
Mbps.  
efficient buffer utilization scheme, reducing  
software tasks and relieving the host CPU from  
performing these housekeeping functions. The  
total memory size is 128 Kbytes (external),  
equivalent to a total chip storage (transmit and  
receive) of 64 outstanding packets.  
FEAST provides a flexible slave interface for  
easy connectivity with industry-standard buses.  
The Bus Interface Unit (BIU) can handle  
synchronous as well as asynchronous buses,  
with different signals being used for each one.  
FEAST's bus interface supports synchronous  
buses like the VESA local bus, as well as burst  
Memory management is handled using a unique  
MMU (Memory Management Unit) architecture  
and a 32-bit wide data path. This I/O mapped  
architecture can sustain back-to-back frame  
transmission and reception for superior data  
throughput and optimal performance. It also  
mode  
DMA  
for  
EISA  
environments.  
Asynchronous bus support for ISA is supported  
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