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L6995S PDF预览

L6995S

更新时间: 2024-02-10 05:11:24
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输出元件输入元件控制器
页数 文件大小 规格书
25页 337K
描述
SWITCHING CONTROLLER, PDSO20, MO-153-AC, TSSOP-20

L6995S 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP20,.25
针数:20Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.82模拟集成电路 - 其他类型:SWITCHING CONTROLLER
控制模式:VOLTAGE-MODE控制技术:PULSE WIDTH MODULATION
最大输入电压:5.5 V最小输入电压:4.5 V
标称输入电压:5 VJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:6.5 mm
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Switching Regulator or Controllers表面贴装:YES
切换器配置:PUSH-PULL温度等级:OTHER
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

L6995S 数据手册

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L6995  
quency after a load transient as well as to mask PWM comparator output against noise and spikes.  
The system has not an internal clock, because this is a hysteretic controller, so the turn on pulse will start if three  
conditions are met contemporarily: the FB pin voltage is lower than the reference voltage, the minimum off time  
is passed and the current limit comparator is not triggered (i.e. the inductor current is below the current limit  
value). The voltage on the OSC pin must range between 50mV and 2V to ensure the system linearity.  
1.2 Closing the loop  
The loop is closed connecting the output voltage (or the output divider middle point) to the FB pin. The FB pin  
is linked internally to the comparator negative pin and the positive pin is connected to the reference voltage  
(0.9V Typ.) as in Figure 2. When the FB goes lower than the reference voltage, the PWM comparator output  
goes high and sets the flip-flop output, turning on the high side MOSFET. This condition is latched to avoid noise  
spike. After the on-time (calculated as described in the previous section) the system resets the flip-flop and then  
turns off the high side MOSFET and turns on the low side MOSFET. Internally the device has more complex  
logic than a flip-flop to manage the transition in correct way. For more details refers to the Figure 1.  
The voltage drop along ground and supply metals connecting output capacitor to the load is a source of DC  
error. Further the system regulates the output voltage valley value not the average, as in the Figure 3 is shown.  
So the voltage ripple on the output capacitor is a source of DC static error (as the PCB traces). To compensate  
the DC errors, an integrator network must be introduced in the control loop, by connecting the output voltage to  
the INT pin through a capacitor and the FB pin to the INT pin directly as in Figure 4. The internal integrator am-  
plifier with the external capacitor C  
for output ripple.  
introduces a DC pole in the control loop. C  
also provides an AC path  
INT1  
INT1  
Figure 3. Valley regulation  
Vout  
DC Error Offset  
<Vout>  
Vref  
Time  
The integrator amplifier generates a current, proportional to the DC errors, that increases the output capacitance  
voltage in order to compensate the total static errors. A voltage clamper within the device forces INT pin voltage  
ranges from V  
-50mV, V +150mV. This is useful to avoid or smooth output voltage overshoot during a load  
REF REF  
transient. Also, this means that the integrator is capable of recovering output error due to ripple when its peak-  
to-peak amplitude is less than 150mV in steady state.  
In case of the ripple amplitude is larger than 150mV, a capacitor C  
can be connected between INT pin and  
INT2  
ground to reduce ripple amplitude at INT pin, otherwise the integrator can operate out of its linear range. Choose  
according to the following equation:  
C
INT1  
g
α
OUT  
INT  
Eq 5  
C
= ---------------------------------  
INT1  
2
π
F
u
where GINT=50 µs is the integrator transconductance,  
is the close loop bandwidth. This equation also holds if C  
is given by:  
α
is the output divider ratio given from Eq4 and F  
OUT  
INT2  
U
is connected between INT pin and ground. C  
INT2  
7/25  

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