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KU80960CA-16 PDF预览

KU80960CA-16

更新时间: 2024-11-27 14:51:55
品牌 Logo 应用领域
英特尔 - INTEL 时钟外围集成电路装置
页数 文件大小 规格书
68页 960K
描述
RISC Microprocessor, 32-Bit, 16MHz, MOS, PQFP196

KU80960CA-16 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QFP, SPQFP196,1.5SQReach Compliance Code:unknown
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.86地址总线宽度:32
位大小:32边界扫描:NO
最大时钟频率:32 MHz外部数据总线宽度:32
格式:FIXED POINT集成缓存:NO
JESD-30 代码:S-PQFP-G196长度:34.29 mm
低功率模式:NO湿度敏感等级:1
DMA 通道数量:4外部中断装置数量:9
串行 I/O 数:端子数量:196
片上数据RAM宽度:8最高工作温度:100 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:SPQFP196,1.5SQ
封装形状:SQUARE封装形式:FLATPACK
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not QualifiedRAM(字数):512
座面最大高度:4.57 mm速度:16 MHz
子类别:Microprocessors最大压摆率:550 mA
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:MOS温度等级:OTHER
端子形式:GULL WING端子节距:0.635 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:34.29 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

KU80960CA-16 数据手册

 浏览型号KU80960CA-16的Datasheet PDF文件第2页浏览型号KU80960CA-16的Datasheet PDF文件第3页浏览型号KU80960CA-16的Datasheet PDF文件第4页浏览型号KU80960CA-16的Datasheet PDF文件第5页浏览型号KU80960CA-16的Datasheet PDF文件第6页浏览型号KU80960CA-16的Datasheet PDF文件第7页 
80960CA-33, -25, -16  
32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR  
• Two Instructions/Clock Sustained Execution  
• Four 59 Mbytes/s DMA Channels with Data Chaining  
• Demultiplexed 32-bit Burst Bus with Pipelining  
32-bit Parallel Architecture  
— Two Instructions/clock Execution  
— Load/Store Architecture  
Four On-Chip DMA Channels  
— 59 Mbytes/s Fly-by Transfers  
— 32 Mbytes/s Two-Cycle Transfers  
— Data Chaining  
— Sixteen 32-bit Global Registers  
— Sixteen 32-bit Local Registers  
— Manipulates 64-bit Bit Fields  
— 11 Addressing Modes  
— Full Parallel Fault Model  
— Supervisor Protection Model  
— Data Packing/Unpacking  
— Programmable Priority Method  
32-Bit Demultiplexed Burst Bus  
— 128-bit Internal Data Paths to and  
from Registers  
Fast Procedure Call/Return Model  
— Burst Bus for DRAM Interfacing  
— Address Pipelining Option  
— Fully Programmable Wait States  
— Supports 8-, 16- or 32-bit Bus Widths  
— Supports Unaligned Accesses  
— Supervisor Protection Pin  
— Full Procedure Call in 4 Clocks  
On-Chip Register Cache  
— Caches Registers on Call/Ret  
— Minimum of 6 Frames Provided  
— Up to 15 Programmable Frames  
Selectable Big or Little Endian Byte  
On-Chip Instruction Cache  
— 1 Kbyte Two-Way Set Associative  
— 128-bit Path to Instruction Sequencer  
— Cache-Lock Modes  
Ordering  
High-Speed Interrupt Controller  
— Up to 248 External Interrupts  
— 32 Fully Programmable Priorities  
— Multi-mode 8-bit Interrupt Port  
— Four Internal DMA Interrupts  
— Separate, Non-maskable Interrupt Pin  
— Context Switch in 750 ns Typical  
— Cache-Off Mode  
High Bandwidth On-Chip Data RAM  
— 1 Kbyte On-Chip Data RAM  
— Sustains 128 bits per Clock Access  
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent  
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.  
© INTEL CORPORATION, 1993  
November 1993  
Order Number: 270727-006  

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