DRAM MODULE
KMM366F80(8)4CS1
CAPACITANCE (TA = 25°C, VCC=3.3V, f = 1MHz)
Item
Symbol
Min
Max
Unit
Input capacitance[A0-A12]
CIN1
CIN2
CIN3
CIN4
CDQ
50
38
24
24
24
pF
pF
pF
pF
pF
-
-
-
-
-
Input capacitance[W0, W2, OE0, OE2]
Input capacitance[RAS0 - RAS3]
Input capacitance[CAS0 - CAS7]
Input/Output capacitance[DQ0-DQ63]
AC CHARACTERISTICS (0°C£TA£70°C, VCC=3.3V±0.3V. See notes 1,2.)
Test condition : Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V, output loading CL=100pF
-5
-6
Parameter
Symbol
Unit
Note
Min
84
Max
Min
104
153
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
tRC
128
tRWC
tRAC
tCAC
tAA
50
13
25
60
15
30
3,4,9
3,4,5
3,9
3
Access time from CAS
Access time from column address
CAS to output in Low-Z
3
3
3
3
tCLZ
tOLZ
tCEZ
tT
OE to output in Low-Z
3
Output buffer turn-off delay from CAS
Transition time(rise and fall)
RAS precharge time
3
13
50
3
13
50
6,12
2
1
1
30
50
8
40
60
10
40
10
20
15
5
tRP
RAS pulse width
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
RAS hold time
CAS hold time
38
8
CAS pulse width
10K
37
10K
45
RAS to CAS delay time
17
12
5
4
9
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
25
30
0
0
7
10
0
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold referenced to CAS
Read command hold referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
0
13
13
7
10
30
0
25
0
0
0
8
8
0
0
7
10
10
10
10
0
7
8
tRWL
tCWL
tDS
7
16
0
Data hold time
7
10
tDH
Refresh period (4K & 8K Ref.)
Write command set-up time
CAS to W delay time
64
64
tREF
tWCS
tCWD
tRWD
0
0
7
7, 15
7
33
70
38
84
RAS to W delay time