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KM48C514DLT-6 PDF预览

KM48C514DLT-6

更新时间: 2024-02-15 00:59:56
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
21页 412K
描述
EDO DRAM, 512KX8, 60ns, CMOS, PDSO28, 0.400 INCH, TSOP2-28

KM48C514DLT-6 技术参数

生命周期:Obsolete零件包装代码:TSOP
包装说明:TSOP2,针数:28
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.84
访问模式:FAST PAGE WITH EDO最长访问时间:60 ns
其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESHJESD-30 代码:R-PDSO-G28
长度:18.41 mm内存密度:4194304 bit
内存集成电路类型:EDO DRAM内存宽度:8
功能数量:1端口数量:2
端子数量:28字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
认证状态:Not Qualified刷新周期:1024
座面最大高度:1.2 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:10.16 mmBase Number Matches:1

KM48C514DLT-6 数据手册

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KM48C514D, KM48V514D  
CMOS DRAM  
512K x 8Bit CMOS Dynamic RAM with Extended Data Out  
DESCRIPTION  
This is a family of 524,288 x 8 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access  
of memory cells within the same row. Power supply voltage(+5.0V or +3.3V), Access time(-5,-6,-7), power consumption(Normal or Low  
power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only  
refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 512Kx8 EDO Mode DRAM  
family is fabricated using Samsung¢s advanced CMOS process to realize high band-width, low power consumption and high reliability.  
It may be used as main memory unit for microcomputer, personal computer and portable machines.  
• Extended Data Out Mode operation  
• Byte Read/Write operation  
FEATURES  
CAS-before-RAS refresh capability  
• Part Identification  
RAS-only and Hidden refresh capability  
- KM48C514D/DL (5V, 1K Ref.)  
- KM48V514D/DL (3.3V, 1K Ref.)  
• Self-refresh capability (L-ver only)  
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs  
• Early Write or output enable controlled write  
Active Power Dissipation  
JEDEC Standard pinout  
Unit : mW  
5V (1K Ref.)  
• Available in 28-pin SOJ 400mil & TSOP(II) 400mil  
packages  
Speed  
-5  
3.3V (1K Ref.)  
-
470  
385  
360  
• Dual +5V±10% power supply(5V product)  
• Dual +3.3V±0.3V power supply(3.3V product)  
-6  
255  
235  
-7  
Refresh Cycles  
FUNCTIONAL BLOCK DIAGRAM  
Part  
VCC  
Refresh  
cycle  
Refresh period  
NO.  
Normal  
L-ver  
RAS  
CAS  
W
Vcc  
Vss  
Control  
Clocks  
C514D  
5V  
VBB Generator  
1K  
16ms  
128ms  
V514D 3.3V  
Data in  
Buffer  
Row Decoder  
Refresh Timer  
Refresh Control  
Performance Range  
Speed  
-5  
Remark  
5V Only  
5V/3.3V  
5V/3.3V  
tRAC  
tCAC  
tRC  
tHPC  
DQ0  
to  
DQ7  
Memory Array  
524,288 x8  
Cells  
50ns 15ns  
84ns 20ns  
Refresh Counter  
Row Address Buffer  
Col. Address Buffer  
-6  
60ns 15ns 104ns 25ns  
70ns 20ns 124ns 30ns  
-7  
A0 - A9  
A0 - A8  
Data out  
Buffer  
Column Decoder  
OE  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  

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