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KM4132G271A-12 PDF预览

KM4132G271A-12

更新时间: 2024-11-23 22:21:55
品牌 Logo 应用领域
三星 - SAMSUNG /
页数 文件大小 规格书
48页 998K
描述
128K x 32Bit x 2 Banks Synchronous Graphic RAM

KM4132G271A-12 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.55
访问模式:DUAL BANK PAGE BURST最长访问时间:9 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:R-PQFP-G100
长度:20 mm内存密度:8388608 bit
内存集成电路类型:SYNCHRONOUS GRAPHICS RAM内存宽度:32
功能数量:1端口数量:1
端子数量:100字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX32封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE认证状态:Not Qualified
座面最大高度:1.4 mm自我刷新:YES
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

KM4132G271A-12 数据手册

 浏览型号KM4132G271A-12的Datasheet PDF文件第2页浏览型号KM4132G271A-12的Datasheet PDF文件第3页浏览型号KM4132G271A-12的Datasheet PDF文件第4页浏览型号KM4132G271A-12的Datasheet PDF文件第5页浏览型号KM4132G271A-12的Datasheet PDF文件第6页浏览型号KM4132G271A-12的Datasheet PDF文件第7页 
KM4132G271A  
CMOS SGRAM  
128K x 32Bit x 2 Banks Synchronous Graphic RAM  
FEATURES  
GENERAL DESCRIPTION  
¡ Ü  
JEDEC standard 3.3V power supply  
The KM4132G271A is 8,388,608 bits synchronous high data  
rate Dynamic RAM organized as 2 x 131,072 words by 32 bits,  
fabricated with SAMSUNG's high performance CMOS technol-  
ogy. Synchronous design allows precise cycle control with the  
use of system clock. I/O transactions are possible on every  
clock cycle. Range of operating frequencies, programmable  
burst length, and programmable latencies allows the same  
device to be useful for a variety of high bandwidth, high perfor-  
mance memory system applications.  
¡ Ü  
LVTTL compatible with multiplexed address  
¡ Ü  
Dual bank / Pulse RAS  
¡ Ü  
MRS cycle with address key programs  
-. CAS Latency (2, 3)  
-. Burst Length (1, 2, 4, 8 & full page)  
-. Burst Type (Sequential & Interleave)  
¡ Ü  
All inputs are sampled at the positive going edge of the  
system clock  
¡ Ü  
Burst Read Single-bit Write operation  
Write per bit and 8 columns block write improves performance in  
graphics systems.  
¡ Ü  
DQM 0-3 for byte masking  
¡ Ü  
Auto & self refresh  
¡ Ü  
16ms refresh period (1K cycle)  
¡ Ü  
100 Pin QFP  
ORDERING INFORMATION  
Graphics Features  
Cycle  
time  
Clock  
f
Access  
time@CL=3  
Part NO.  
¡ Ü  
SMRS cycle.  
-. Load mask register  
-. Load color register  
KM4132G271A-8  
KM4132G271A-10  
KM4132G271A-12  
8ns  
125MHz  
100MHz  
83MHz  
7.0ns  
7.0ns  
9.0ns  
10ns  
12ns  
¡ Ü  
Write Per Bit(Old Mask)  
¡ Ü  
Block Write(8 Columns)  
FUNCTIONAL BLOCK DIAGRAM  
MASK  
REGISTER  
DQMi  
BLOCK  
COLOR  
REGISTER  
WRITE  
CONTROL  
LOGIC  
WRITE  
CONTROL  
LOGIC  
MUX  
CLK  
CKE  
CS  
COLUMN  
MASK  
DQi  
(i=0~31)  
DQMi  
RAS  
CAS  
WE  
128Kx32  
CELL  
128Kx32  
CELL  
ARRAY  
ARRAY  
DSF  
DQMi  
ROW DECORDER  
BANK SELECTION  
SERIAL  
COUNTER  
COLUMN ADDRESS  
BUFFER  
ROW ADDRESS  
BUFFER  
REFRESH  
COUNTER  
ADDRESS REGISTER  
CLOCK ADDRESS(A0~A9)  
Rev.0 (August 1997)  

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