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KM23V8105DT-10 PDF预览

KM23V8105DT-10

更新时间: 2024-11-25 14:43:03
品牌 Logo 应用领域
三星 - SAMSUNG 有原始数据的样本ROM光电二极管内存集成电路
页数 文件大小 规格书
5页 88K
描述
MASK ROM, 512KX16, 100ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44

KM23V8105DT-10 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2, TSOP44,.46,32
针数:44Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.45最长访问时间:100 ns
备用内存宽度:8JESD-30 代码:R-PDSO-G44
JESD-609代码:e0长度:18.41 mm
内存密度:8388608 bit内存集成电路类型:MASK ROM
内存宽度:16功能数量:1
端子数量:44字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX16封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP44,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3/3.3 V认证状态:Not Qualified
座面最大高度:1.2 mm最大待机电流:0.00003 A
子类别:MASK ROMs最大压摆率:0.04 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.16 mm
Base Number Matches:1

KM23V8105DT-10 数据手册

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KM23V8105D(E)T  
CMOS MASK ROM  
8M-Bit (1Mx8 /512Kx16) CMOS MASK ROM  
FEATURES  
GENERAL DESCRIPTION  
· Switchable organization  
1,048,576 x 8(byte mode)  
524,288 x 16(word mode)  
· Random Access Time/Page Access Time  
3.3V Operation : 100/30ns(Max.)  
3.0V Operation : 120/40ns(Max.)  
· 4 Words / 8 bytes page access  
· Supply voltage : single +3.0V/single +3.3V  
· Current consumption  
The KM23V8105D(E)T is a fully static mask programmable  
ROM fabricated using silicon gate CMOS process technology,  
and is organized either as 1,048,576 x 8 bit(byte mode) or as  
524,288 x 16 bit(word mode) depending on BHE voltage  
level.(See mode selection table)  
This device includes page read mode function, page read mode  
allows 4 words (or 8bytes) of data to read fast in the same  
page, CE and A2 ~ A18 should not be changed.  
This device operates with a 3.0V or 3.3V power supply, and all  
inputs and outputs are TTL compatible.  
Operating : 40mA(Max.)  
Standby : 30mA(Max.)  
· Fully static operation  
· All inputs and outputs TTL compatible  
· Three state outputs  
· Package  
-. KM23V8105D(E)T : 44-TSOP2-400  
Because of its asynchronous operation, it requires no external  
clock assuring extremely easy operation.  
It is suitable for use in program memory of microprocessor, and  
data memory, character generator.  
The KM23V8105D(E)T is packaged in a 44-TSOP2.  
FUNCTIONAL BLOCK DIAGRAM  
PRODUCT INFORMATION  
Operating  
Temp Range  
Vcc Range  
(Typical)  
Speed  
(ns)  
Product  
A18  
X
MEMORY CELL  
MATRIX  
KM23V8105DT  
0°C~70°C  
BUFFERS  
AND  
100/30ns  
120/40ns  
.
.
.
.
.
.
.
.
3.3V/3.0V  
(524,288x16/  
1,048,576x8)  
KM23V8105DET  
-20°C~85°C  
DECODER  
PIN CONFIGURATION  
Y
SENSE AMP.  
BUFFERS  
AND  
DATA OUT  
BUFFERS  
DECODER  
A2  
N.C  
A18  
A17  
A7  
1
2
44 N.C  
N.C  
A8  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
3
A0~A1  
A-1  
. . .  
4
A9  
A6  
A10  
A11  
A12  
5
CE  
A5  
6
Q0/Q8  
Q7/Q15  
CONTROL  
LOGIC  
OE  
A4  
7
A3  
8
A13  
A14  
BHE  
A2  
9
A1  
A15  
10  
11  
12  
13  
14  
15  
16  
17  
18  
Pin Name  
A0 - A1  
Pin Function  
A0  
A16  
TSOP2  
BHE  
VSS  
CE  
VSS  
OE  
Q0  
Page Address Inputs  
Address Inputs  
Data Outputs  
A2- A18  
Q15/A-1  
Q7  
Q0 - Q14  
Output 15(Word mode)/  
LSB Address(Byte mode)  
Q8  
29 Q14  
28 Q6  
Q15 /A-1  
Q1  
BHE  
CE  
Word/Byte selection  
Chip Enable  
Output Enable  
Power  
Q9  
Q13  
Q5  
27  
26  
25  
24  
23  
Q2 19  
Q10 20  
Q12  
Q4  
OE  
Q3  
21  
22  
VCC  
VSS  
N.C  
Q11  
VCC  
Ground  
No Connection  
KM23V8105D(E)T  

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