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KA3882EDTF PDF预览

KA3882EDTF

更新时间: 2024-11-26 20:07:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 开关光电二极管
页数 文件大小 规格书
6页 46K
描述
Switching Controller, Current-mode, 1A, 500kHz Switching Freq-Max, BIPolar, PDSO8, SOIC-8

KA3882EDTF 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, DIP8,.3
针数:8Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.66模拟集成电路 - 其他类型:SWITCHING CONTROLLER
控制模式:CURRENT-MODE控制技术:PULSE WIDTH MODULATION
最大输入电压:25 V最小输入电压:12 V
标称输入电压:15 VJESD-30 代码:R-PDSO-G8
JESD-609代码:e0功能数量:1
端子数量:8最高工作温度:70 °C
最低工作温度:最大输出电流:1 A
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:DIP8,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified子类别:Switching Regulator or Controllers
表面贴装:YES切换器配置:SINGLE
最大切换频率:500 kHz技术:BIPOLAR
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

KA3882EDTF 数据手册

 浏览型号KA3882EDTF的Datasheet PDF文件第2页浏览型号KA3882EDTF的Datasheet PDF文件第3页浏览型号KA3882EDTF的Datasheet PDF文件第4页浏览型号KA3882EDTF的Datasheet PDF文件第5页浏览型号KA3882EDTF的Datasheet PDF文件第6页 
www.fairchildsemi.com  
KA3882E/KA3883E  
SMPS Controller  
Features  
Description  
• Low start current 0.2mA (typ)  
• Operating range up to 500kHz  
• Cycle by cycle current limiting  
• Under voltage lock out with hysteresis  
• Short shutdown delay time: typ.100ns  
• High current totem-pole output  
• Output swing limiting: 22V  
The KA3882E/KA3883E is a fixed PWM controller for  
Off-Line and DC to DC converter applications. The internal  
circuits include a UVLO, a low start-up current circuit, a  
temperature compensated reference, a high gain error  
amplifier, a current sensing comparator, and the high current  
totem-pole output for driving a POWER MOSFET. Also the  
KA3882E/KA3883E provides low start-up current below  
0.3mA and short shutdown delay time typ. 100ns. The  
KA3882E has UVLO threshold of 16V(on) and 10V(off).  
The KA3883E is 8.4V(on) and 7.6V(off). The KA3882E and  
KA3883E can operate within 100% duty cycle.  
8-DIP  
1
8-SOP  
1
Internal Block Diagram  
7
5
V
CC  
29V  
5V  
SET/  
RESET  
VREF  
8
V
REF  
GND  
UVLO  
Internal  
Bias  
Good LOGIC  
PWR  
7
6
5
VC  
1/2VREF  
C.S  
Comp.  
PWM  
Error Amp  
+
-
LATCH  
1/3  
1V  
VFB  
2
R
S
22V  
OUTPUT  
1
3
COMP  
C.S  
PWR  
GND  
R
T/C  
T
OSCILLATOR  
4
Rev. 1.0.1  
©2003 Fairchild Semiconductor Corporation  

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