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K9F1208B0C-PCB0T PDF预览

K9F1208B0C-PCB0T

更新时间: 2024-01-08 01:34:19
品牌 Logo 应用领域
三星 - SAMSUNG 光电二极管内存集成电路
页数 文件大小 规格书
38页 824K
描述
Flash, 64MX8, 30ns, PDSO48

K9F1208B0C-PCB0T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:TSSOP, TSSOP48,.8,20
Reach Compliance Code:compliant风险等级:5.76
最长访问时间:30 ns命令用户界面:YES
数据轮询:NOJESD-30 代码:R-PDSO-G48
JESD-609代码:e3内存密度:536870912 bit
内存集成电路类型:FLASH内存宽度:8
湿度敏感等级:1部门数/规模:4K
端子数量:48字数:67108864 words
字数代码:64000000最高工作温度:70 °C
最低工作温度:组织:64MX8
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP48,.8,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH页面大小:512 words
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:2.7 V认证状态:Not Qualified
就绪/忙碌:YES部门规模:16K
最大待机电流:0.00005 A子类别:Flash Memories
最大压摆率:0.02 mA标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
切换位:NO

K9F1208B0C-PCB0T 数据手册

 浏览型号K9F1208B0C-PCB0T的Datasheet PDF文件第5页浏览型号K9F1208B0C-PCB0T的Datasheet PDF文件第6页浏览型号K9F1208B0C-PCB0T的Datasheet PDF文件第7页浏览型号K9F1208B0C-PCB0T的Datasheet PDF文件第9页浏览型号K9F1208B0C-PCB0T的Datasheet PDF文件第10页浏览型号K9F1208B0C-PCB0T的Datasheet PDF文件第11页 
K9F1208U0C  
K9F1208R0C K9F1208B0C  
FLASH MEMORY  
Figure 1. K9F1208X0C FUNCTIONAL BLOCK DIAGRAM  
VCC  
VSS  
X-Buffers  
A9 - A25  
512M + 16M Bits  
Latches  
NAND Flash  
ARRAY  
& Decoders  
Y-Buffers  
Latches  
A0 - A7  
& Decoders  
(512 + 16)Bytes x 131,072  
Page Register & S/A  
Y-Gating  
A8  
Command  
Command  
Register  
I/O Buffers & Latches  
Global Buffers  
VCC  
VSS  
CE  
RE  
WE  
Control Logic  
& High Voltage  
Generator  
I/0 0  
I/0 7  
Output  
Driver  
CLE ALE  
WP  
Figure 2. K9F1208X0C ARRAY ORGANIZATION  
1 Block = 32 Pages  
= (16K + 512) Bytes  
1 Page = 528 Bytes  
1 Block = 528 Bytes x 32 Pages  
= (16K + 512) Bytes  
1 Device = 528Bytes x 32Pages x 4,096 Blocks  
= 528 Mbits  
128K Pages  
(=4,096 Blocks)  
1st half Page Register  
(=256 Bytes)  
2nd half Page Register  
(=256 Bytes)  
8 bits  
512Bytes  
16 Bytes  
16 Bytes  
I/O 0 ~ I/O 7  
Page Register  
512 Bytes  
I/O 0  
A0  
I/O 1  
A1  
I/O 2  
A2  
I/O 3  
I/O 4  
I/O 5  
A5  
I/O 6  
A6  
I/O 7  
A7  
1st Cycle  
2nd Cycle  
3rd Cycle  
4th Cycle  
A3  
A12  
A20  
*L  
A4  
A13  
A21  
*L  
Column Address  
Row Address  
(Page Address)  
A9  
A10  
A18  
*L  
A11  
A19  
*L  
A14  
A22  
*L  
A15  
A23  
*L  
A16  
A24  
*L  
A17  
A25  
NOTE : Column Address : Starting Address of the Register.  
00h Command(Read) : Defines the starting address of the 1st half of the register.  
01h Command(Read) : Defines the starting address of the 2nd half of the register.  
* A8 is set to "Low" or "High" by the 00h or 01h Command.  
* L must be set to "Low".  
* The device ignores any additional input of address cycles than reguired.  
8

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