K7B803625B
K7B801825B
256Kx36 & 512Kx18 Synchronous SRAM
PIN CONFIGURATION(TOP VIEW)
DQPc
1
DQPb
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc0
2
DQc1
3
VDDQ
4
VSSQ
5
DQc2
6
DQc3
7
DQc4
8
DQc5
9
VSSQ
10
VDDQ
11
DQc6
12
100 Pin TQFP
DQc7
13
N.C.
14
VDD
15
N.C.
(20mm x 14mm)
N.C.
16
VDD
ZZ
VSS
17
DQd0
18
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa
K7B803625B(256Kx36)
DQd1
19
VDDQ
20
VSSQ
21
DQd2
22
DQd3
23
DQd4
24
DQd5
25
VSSQ
26
VDDQ
27
DQd6
28
DQd7
29
DQPd
30
PIN
SYMBOL
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A17
32,33,34,35,36,37,43 VDD
44,45,46,47,48,49,50 VSS
81,82,99,100
83
Power Supply(+3.3V) 15,41,65,91
Ground
No Connect
17,40,67,90
14,16,38,39,42,66
N.C.
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
Burst Address Advance
Address Status Processor 84
Address Status Controller 85
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
Clock
89
Chip Select
Chip Select
Chip Select
98
97
92
WEx(x=a,b,c,d) Byte Write Inputs
93,94,95,96
VDDQ
VSSQ
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V or 3.3V)
Output Ground
OE
Output Enable
86
88
87
64
31
GW
BW
ZZ
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
5,10,21,26,55,60,71,76
LBO
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
2. The pin 42 is reserved for address bit for the 16Mb .
Rev. 6.0 April 2006
- 5 -