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K6R4016V1D-UI100 PDF预览

K6R4016V1D-UI100

更新时间: 2024-02-15 10:40:04
品牌 Logo 应用领域
三星 - SAMSUNG 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
12页 224K
描述
Standard SRAM, 256KX16, 10ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, TSOP2-44

K6R4016V1D-UI100 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2, TSOP44,.46,32针数:44
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.82
最长访问时间:10 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G44长度:18.41 mm
内存密度:4194304 bit内存集成电路类型:STANDARD SRAM
内存宽度:16湿度敏感等级:2
功能数量:1端子数量:44
字数:262144 words字数代码:256000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:256KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP44,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.2 mm最大待机电流:0.005 A
最小待机电流:3 V子类别:SRAMs
最大压摆率:0.075 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:10.16 mm
Base Number Matches:1

K6R4016V1D-UI100 数据手册

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PRELIMPreliminaryPPPPPPPPPINARY  
CMOS SRAM  
K6R4016V1D  
AC CHARACTERISTICS(TA=0 to 70°C, VCC=3.3±0.3V, unless otherwise noted.)  
TEST CONDITIONS*  
Parameter  
Value  
Input Pulse Levels  
0V to 3V  
3ns  
Input Rise and Fall Times  
Input and Output timing Reference Levels  
Output Loads  
1.5V  
See below  
* The above test conditions are also applied at industrial temperature range.  
Output Loads(B)  
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ  
Output Loads(A)  
+3.3V  
RL = 50Ω  
DOUT  
319Ω  
VL = 1.5V  
DOUT  
30pF*  
ZO = 50Ω  
353Ω  
5pF*  
* Capacitive Load consists of all components of the  
test environment.  
* Including Scope and Jig Capacitance  
READ CYCLE*  
K6R4016V1D-08  
K6R4016V1D-10  
Min Max  
Parameter  
Symbol  
Unit  
Min  
8
-
Max  
Read Cycle Time  
tRC  
tAA  
-
8
8
4
4
-
10  
-
-
10  
10  
5
5
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
Chip Select to Output  
tCO  
tOE  
tBA  
-
-
Output Enable to Valid Output  
UB, LB Access Time  
-
-
-
-
Chip Enable to Low-Z Output  
Output Enable to Low-Z Output  
UB, LB Enable to Low-Z Output  
Chip Disable to High-Z Output  
Output Disable to High-Z Output  
UB, LB Disable to High-Z Output  
Output Hold from Address Change  
Chip Selection to Power Up Time  
Chip Selection to Power DownTime  
tLZ  
3
0
0
0
0
0
3
0
-
3
0
0
0
0
0
3
0
-
tOLZ  
tBLZ  
tHZ  
-
-
-
-
4
4
4
-
5
5
5
-
tOHZ  
tBHZ  
tOH  
tPU  
-
-
tPD  
8
10  
* The above parameters are also guaranteed at industrial temperature range.  
Rev 4.0  
Mar. 2004  
- 6 -  

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