PRELIMPreliminaryPPPPPPPPPINARY
CMOS SRAM
K6R4016V1C-C/C-L, K6R4016V1C-I/C-P
256K x 16 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 10,12,15ns(Max.)
• Low Power Dissipation
Standby (TTL)
(CMOS) : 10mA(Max.)
1.2mA(Max.) L-Ver. only
Operating K6R4016V1C-10 : 160mA(Max.)
K6R4016V1C-12 : 150mA(Max.)
K6R4016V1C-15 : 140mA(Max.)
• Single 3.3 ±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
GENERAL DESCRIPTION
The K6R4016V1C is a 4,194,304-bit high-speed Static Random
Access Memory organized as 262,144 words by 16 bits. The
K6R4016V1C uses 16 common input and output lines and has
an output enable pin which operates faster than address
access time at read cycle. Also it allows that lower and upper
byte access by data byte control(UB, LB). The device is fabri-
cated using SAMSUNG¢s advanced CMOS process and
designed for high-speed circuit technology. It is particularly well
suited for use in high-density high-speed system applications.
The K6R4016V1C is packaged in a 400mil 44-pin plastic SOJ
or TSOP(II) forward or 48 Fine pitch BGA.
: 60mA(Max.)
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention : L-Ver. only
• Center Power/Ground Pin Configuration
• Data Byte Control : LB : I/O1~ I/O8, UB : I/O9~ I/O16
• Standard Pin Configuration
K6R4016V1C-J : 44-SOJ-400
K6R4016V1C-T : 44-TSOP2-400BF
K6R4016V1C-F : 48-Fine pitch BGA with 0.75 Ball pitch
ORDERING INFORMATION
FUNCTIONAL BLOCK DIAGRAM
K6R4016V1C-C10/C12/C15
Commercial Temp.
Industrial Temp.
K6R4016V1C-I10/I12/I15
Clk Gen.
Pre-Charge Circuit
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Memory Array
1024 Rows
256 x 16 Columns
Data
Cont.
I/O Circuit &
Column Select
I/O1~I/O8
Data
Cont.
I/O9~I/O16
Gen.
CLK
A10 A11 A12 A13 A14 A15 A16 A17
WE
OE
UB
LB
CS
Rev 5.0
September 2001
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