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K4S280832D-NL7C PDF预览

K4S280832D-NL7C

更新时间： 2024-02-26 23:21:31
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
11页 113K
描述
Synchronous DRAM, 16MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54

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K4S280832D-NL7C 技术参数

生命周期：Obsolete零件包装代码：TSOP2
包装说明：TSOP,针数：54
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.02风险等级：5.83
访问模式：FOUR BANK PAGE BURST最长访问时间：5.4 ns
其他特性：AUTO/SELF REFRESHJESD-30 代码：R-PDSO-G54
长度：11.2 mm内存密度：134217728 bit
内存集成电路类型：SYNCHRONOUS DRAM内存宽度：8
功能数量：1端口数量：1
端子数量：54字数：16777216 words
字数代码：16000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：16MX8封装主体材料：PLASTIC/EPOXY
封装代码：TSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE认证状态：Not Qualified
座面最大高度：1.2 mm自我刷新：YES
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.4 mm
端子位置：DUAL宽度：10.16 mm
Base Number Matches：1

K4S280832D-NL7C 数据手册

 浏览型号K4S280832D-NL7C的Datasheet PDF文件第5页浏览型号K4S280832D-NL7C的Datasheet PDF文件第6页浏览型号K4S280832D-NL7C的Datasheet PDF文件第7页浏览型号K4S280832D-NL7C的Datasheet PDF文件第8页浏览型号K4S280832D-NL7C的Datasheet PDF文件第9页浏览型号K4S280832D-NL7C的Datasheet PDF文件第10页 
K4S280832D  
CMOS SDRAM  
SIMPLIFIED TRUTH TABLE  
A11,  
A9 ~ A0  
Command  
CKEn-1  
CKEn  
CS  
RAS  
CAS  
WE  
DQM BA0,1  
A10/AP  
Note  
Register  
Refresh  
Mode register set  
Auto refresh  
H
X
H
L
L
L
L
L
X
OP code  
1,2  
3
H
L
L
L
L
H
X
X
X
X
Entry  
3
Self  
L
H
L
H
X
L
H
X
H
H
X
H
3
Refresh  
Exit  
H
3
Bank active & row addr.  
H
H
X
X
X
X
V
V
Row address  
Column  
address  
(A0 ~ A9)  
Read &  
column address  
Auto precharge disable  
Auto precharge enable  
Auto precharge disable  
Auto precharge enable  
L
H
L
4
4,5  
4
L
L
H
H
L
L
H
L
Column  
address  
(A0 ~ A9)  
Write &  
column address  
H
X
X
V
H
X
L
4,5  
6
Burst stop  
Precharge  
H
H
X
X
L
L
H
L
H
H
L
L
X
X
Bank selection  
All banks  
V
X
X
H
H
L
X
V
X
X
H
X
V
X
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry  
H
L
X
Clock suspend or  
active power down  
X
X
Exit  
L
H
L
X
H
L
X
X
Entry  
H
Precharge power down mode  
H
L
Exit  
L
H
X
X
DQM  
H
H
V
X
X
X
7
H
L
X
H
X
H
X
H
No operation command  
(V=Valid, X=Don¢t care, H=Logic high, L=Logic low)  
Notes :  
1. OP Code : Operand code  
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)  
2. MRS can be issued only at all banks precharge state.  
A new command can be issued after 2 CLK cycles of MRS.  
3. Auto refresh functions are as same as CBR refresh of DRAM.  
The automatical precharge without row precharge command is meant by "Auto".  
Auto/self refresh can be issued only at all banks precharge state.  
4. BA0 ~ BA1 : Bank select addresses.  
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.  
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.  
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.  
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.  
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.  
5. During burst read or write with auto precharge, new read/write command can not be issued.  
Another bank read/write command can be issued after the end of burst.  
New row active of the associated bank can be issued at tRP after the end of burst.  
6. Burst stop command is valid at every burst length.  
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),  
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)  
Rev. 0.1 Sept. 2001  
1...891011

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与K4S280832D-NL7C相关器件

型号 品牌 获取价格 描述 数据表
K4S280832D-TB1H SAMSUNG

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 		Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
K4S280832D-TB75 SAMSUNG

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 		Synchronous DRAM, 16MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
K4S280832D-TC/L1H SAMSUNG

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 		128Mbit SDRAM (4M x 8Bit x 4 Banks Synchronous DRAM)
K4S280832D-TC/L1L SAMSUNG

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 		128Mbit SDRAM (4M x 8Bit x 4 Banks Synchronous DRAM)
K4S280832D-TC/L75 SAMSUNG

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 		128Mbit SDRAM (4M x 8Bit x 4 Banks Synchronous DRAM)
K4S280832D-TC/L7C SAMSUNG

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 		128Mbit SDRAM (4M x 8Bit x 4 Banks Synchronous DRAM)
K4S280832D-TC1H SAMSUNG

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 		Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
K4S280832D-TC1L SAMSUNG

获取价格

 		Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
K4S280832D-TC75 SAMSUNG

获取价格

 		Synchronous DRAM, 16MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
K4S280832D-TC7C SAMSUNG

获取价格

 		Synchronous DRAM, 16MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

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