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K4F171612C-JC50T PDF预览

K4F171612C-JC50T

更新时间: 2024-02-04 08:00:39
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
34页 894K
描述
Fast Page DRAM, 1MX16, 50ns, CMOS, PDSO42,

K4F171612C-JC50T 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SOJ, SOJ42,.44Reach Compliance Code:compliant
风险等级:5.92最长访问时间:50 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-J42
内存密度:16777216 bit内存集成电路类型:FAST PAGE DRAM
内存宽度:16端子数量:42
字数:1048576 words字数代码:1000000
最高工作温度:70 °C最低工作温度:
组织:1MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ42,.44封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:3.3 V
认证状态:Not Qualified刷新周期:4096
自我刷新:NO最大待机电流:0.0005 A
子类别:DRAMs最大压摆率:0.09 mA
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

K4F171612C-JC50T 数据手册

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K4F171611C, K4F151611C  
K4F171612C, K4F151612C  
CMOS DRAM  
1M x 16Bit CMOS Dynamic RAM with Fast Page Mode  
DESCRIPTION  
This is a family of 1,048,576 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory  
cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K Ref.), access time (-50 or -60), power  
consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-  
before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This  
1Mx16 Fast Page Mode DRAM family is fabricated using Samsung¢s advanced CMOS process to realize high band-width, low power  
consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.  
FEATURES  
• Part Identification  
• Fast Page Mode operation  
• 2 CAS Byte/Word Read/Write operation  
• CAS-before-RAS refresh capability  
- K4F171611C-J(T) (5V, 4K Ref.)  
• RAS-only and Hidden refresh capability  
- K4F151611C-J(T) (5V, 1K Ref.)  
• Self-refresh capability (L-ver only)  
- K4F171612C-J(T) (3.3V, 4K Ref.)  
- K4F151612C-J(T) (3.3V, 1K Ref.)  
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs  
• Early Write or output enable controlled write  
• JEDEC Standard pinout  
Active Power Dissipation  
Unit : mW  
5V  
• Available in 42-pin SOJ 400mil and 50(44)-pin TSOP(II)  
3.3V  
Speed  
400mil packages  
• Single +5V±10% power supply (5V product)  
4K  
1K  
4K  
495  
440  
1K  
-50  
-60  
324  
288  
504  
468  
770  
715  
• Single +3.3V±0.3V power supply (3.3V product)  
FUNCTIONAL BLOCK DIAGRAM  
Refresh Cycles  
Part  
NO.  
Refresh Refresh period  
VCC  
RAS  
UCAS  
LCAS  
W
Vcc  
Vss  
cycle  
Normal  
L-ver  
Control  
Clocks  
VBB Generator  
K4F171611C  
5V  
4K  
64ms  
K4F171612C 3.3V  
K4F151611C 5V  
Lower  
Data in  
Buffer  
128ms  
DQ0  
to  
DQ7  
Row Decoder  
Refresh Timer  
Refresh Control  
1K  
16ms  
K4F151612C 3.3V  
Lower  
Data out  
Buffer  
Memory Array  
1,048,576 x16  
Cells  
OE  
Refresh Counter  
Row Address Buffer  
Col. Address Buffer  
Upper  
Data in  
Buffer  
Perfomance Range  
A0-A11  
(A0 - A9)*1  
A0 - A7  
DQ8  
to  
DQ15  
Speed  
-50  
Remark  
tRAC  
50ns  
60ns  
tCAC  
tRC  
tPC  
Upper  
Data out  
Buffer  
15ns  
90ns  
35ns 5V/3.3V  
Column Decoder  
(A0 - A9)*1  
-60  
15ns 110ns 40ns 5V/3.3V  
Note) *1 : 1K Refresh  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  

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