5秒后页面跳转
JM3851012501SGA PDF预览

JM3851012501SGA

更新时间: 2024-11-24 12:04:39
品牌 Logo 应用领域
德州仪器 - TI 采样保持电路
页数 文件大小 规格书
21页 1015K
描述
LF198JAN Monolithic Sample-and-Hold Circuits

JM3851012501SGA 数据手册

 浏览型号JM3851012501SGA的Datasheet PDF文件第2页浏览型号JM3851012501SGA的Datasheet PDF文件第3页浏览型号JM3851012501SGA的Datasheet PDF文件第4页浏览型号JM3851012501SGA的Datasheet PDF文件第5页浏览型号JM3851012501SGA的Datasheet PDF文件第6页浏览型号JM3851012501SGA的Datasheet PDF文件第7页 
LF198JAN  
www.ti.com  
SNOSAJ2A FEBRUARY 2005REVISED MARCH 2013  
LF198JAN Monolithic Sample-and-Hold Circuits  
Check for Samples: LF198JAN  
1
FEATURES  
DESCRIPTION  
The LF198 is a monolithic sample-and-hold circuit  
which utilizes BI-FET technology to obtain ultra-high  
dc accuracy with fast acquisition of signal and low  
droop rate. Operating as a unity gain follower, dc gain  
accuracy is 0.002% typical and acquisition time is as  
low as 6 μs to 0.01%. A bipolar input stage is used to  
achieve low offset voltage and wide bandwidth. Input  
offset adjust is accomplished with a single pin, and  
does not degrade input offset drift. The wide  
bandwidth allows the LF198 to be included inside the  
feedback loop of 1 MHz op amps without having  
stability problems. Input impedance of 1010Ω allows  
high source impedances to be used without  
degrading accuracy.  
2
Operates from ±5V to ±18V Supplies  
Less Than 10 μs Acquisition Time  
TTL, PMOS, CMOS Compatible Logic Input  
0.5 mV Typical Hold Step at Ch = 0.01 μF  
Low Input Offset  
0.002% Gain Accuracy  
Low Output Noise in Hold Mode  
Input Characteristics Do Not Change During  
Hold Mode  
High Supply Rejection Ratio in Sample or Hold  
Wide Bandwidth  
Space Qualified  
P-channel junction FET's are combined with bipolar  
devices in the output amplifier to give droop rates as  
low as 5 mV/min with a 1 μF hold capacitor. The  
JFET's have much lower noise than MOS devices  
used in previous designs and do not exhibit high  
temperature instabilities. The overall design ensures  
no feed-through from input to output in the hold  
mode, even for input signals equal to the supply  
voltages.  
Logic Inputs on the LF198 are Fully Differential  
with Low Input Current, Allowing Direct  
Connection to TTL, PMOS, and CMOS.  
Differential Threshold is 1.4V. The LF198 will  
Operate from ±5V to ±18V Supplies.  
Connection Diagrams  
Figure 1. TO-99 Package  
See Package Number LMC  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005–2013, Texas Instruments Incorporated  

与JM3851012501SGA相关器件

型号 品牌 获取价格 描述 数据表
JM3851012908BPA TI

获取价格

DUAL PERIPHERAL DRIVERS
JM3851012909BPA TI

获取价格

DUAL PERIPHERAL DRIVERS
JM3851013506BPA TI

获取价格

LOW-NOISE HIGH-SPEED PRECISION OPERATIONAL AMPLIFIERS
JM3851017203BCA TI

获取价格

CMOS Quad Exclusive-OR and Exclusive-NOR Gate
JM38510-30001BCA TI

获取价格

QUADRUPLE 2-INPUT POSITIVE-NAND GATES
JM3851030102B2A TI

获取价格

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLIP-FLOPS WITH PRESET AND CLEAR
JM3851030102BCA TI

获取价格

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLIP-FLOPS WITH PRESET AND CLEAR
JM3851030102BDA TI

获取价格

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLIP-FLOPS WITH PRESET AND CLEAR
JM3851030102SCA TI

获取价格

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLIP-FLOPS WITH PRESET AND CLEAR
JM3851030102SDA TI

获取价格

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLIP-FLOPS WITH PRESET AND CLEAR