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JM38510/11105BIA PDF预览

JM38510/11105BIA

更新时间： 2024-02-28 21:48:56
品牌 Logo 应用领域
威世 - VISHAY /
页数 文件大小 规格书
9页 87K
描述
IC 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, MBCY10, METAL CAN-10, Multiplexer or Switch

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中文翻译

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JM38510/11105BIA 技术参数

是否无铅：含铅生命周期：Active
零件包装代码：BCY包装说明：,
针数：10Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.55
Is Samacsys：N其他特性：FAULT PROTECTED
模拟集成电路 - 其他类型：SPDTJESD-30 代码：O-MBCY-W10
JESD-609代码：e0标称负供电电压 (Vsup)：-15 V
信道数量：1功能数量：1
端子数量：10标称断态隔离度：50 dB
最大通态电阻 (Ron)：30 Ω最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：METAL
封装形状：ROUND封装形式：CYLINDRICAL
认证状态：Not Qualified筛选级别：MIL-M-38510
标称供电电压 (Vsup)：15 V表面贴装：NO
最长断开时间：130 ns最长接通时间：150 ns
技术：JFET温度等级：MILITARY
端子面层：TIN LEAD端子形式：WIRE
端子位置：BOTTOMBase Number Matches：1

JM38510/11105BIA 数据手册

 浏览型号JM38510/11105BIA的Datasheet PDF文件第2页浏览型号JM38510/11105BIA的Datasheet PDF文件第3页浏览型号JM38510/11105BIA的Datasheet PDF文件第4页浏览型号JM38510/11105BIA的Datasheet PDF文件第5页浏览型号JM38510/11105BIA的Datasheet PDF文件第6页浏览型号JM38510/11105BIA的Datasheet PDF文件第7页 
DG186/187/188  
Vishay Siliconix  
High-Speed Drivers with SPDT JFET Switches  
FEATURES  
BENEFITS  
APPLICATIONS  
D Constant On-Resistance Over  
D Low Distortion  
D Audio Switching  
D Video Switching  
D Sample/Hold  
Entire Analog Range  
D Eliminates Large Signal Errors  
D High Precision  
D Low Leakage  
D Low Crosstalk  
D Rad Hardness  
D High Bandwidth Capability  
D Fault Protection  
D Guidance and Control Systems  
D Telemetry  
DESCRIPTION  
The DG186/187/188 are precision single-pole, double-throw  
(SPDT) analog switches designed to provide accurate  
switching of video and audio signals. This series is ideally  
suited for applications requiring a constant on-resistance over  
the entire analog range.  
on-resistance include audio switching, video switching, and  
data acquisition.  
To achieve fast and accurate switch performance, each device  
comprises two n-channel JFET transistors and a TTL  
compatible bipolar driver. The driver is designed to achieve  
break-before-make switching action, eliminating the  
inadvertent shorting between channels and the crosstalk  
which would result. In the on state, each switch conducts  
current equally well in either direction. In the off condition, the  
switches will block up to 20 V peak-to-peak, with feedthrough  
of less than –60 dB at 10 MHz.  
The major difference in the devices is the on-resistance  
(DG186—10 W, DG187—30 W, DG188—75 W). Reduced  
errors are achieved through low leakage current (ID(on)  
< 2 nA). Applications which benefit from the flat JFET  
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION  
D
2
NC  
NC  
NC  
NC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
NC  
NC  
NC  
NC  
D2  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
Dual-In-Line  
Top View  
D
S
1
2
Flat  
Package  
10  
D
1
D
2
1
4
9
6
S
1
S
2
S
D
1
NC  
1
Top View  
2
3
8
IN  
NC  
S
1
S
2
V+  
V–*  
7
V–*  
IN  
NC  
V–  
IN  
V
L
V
R
8
Metal Can  
Top View  
V+  
5
V+  
V
R
Refer to JAN38510 Information, Military Section  
V
L
V
R
8
V
L
*COMMON TO SUBSTRATE AND CASE  
TRUTH TABLE  
Logic  
SW1  
OFF  
ON  
SW2  
ON  
0
1
OFF  
Logic “0” v 0.8 V  
Logic “1”
w
w 2.0 V  
Document Number: 70033  
S-52895—Rev. E, 16-Jun-97  
www.vishay.com S FaxBack 408-970-5600  
4-1  
1234567...9

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 		High-Speed Drivers with Dual SPDT JFET Switches

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