Datasheet > JCLNLATN@50.000MHZ

JCLNLATN@50.000MHZ

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
美高森美 - MICROSEMI		/
页数	文件大小	规格书
10页	200K
描述
CMOS/TTL Output Clock Oscillator, 1.024MHz Min, 155.52MHz Max, 50MHz Nom, HERMETIC SEALDED, J-LEADED, CERAMIC PACKAGE-6

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J-Type Voltage Controlled Crystal Oscillator

Table 1. Pin Out Information for the CMOS output Option

Symbol

Function

V_C

VCXO Control Voltage

TTL logic low disables output.

Tri-State¹

TOP VIEW

TTL logic high, or no connect, enables output.

GND

Output

CMOS/TTL

select^1,2

V_CC

Case and Electrical Ground

VCXO Output

TTL logic low optimizes symmetry for CMOS.

TTL logic high, or NC, optimizes symmetry for TTL

Power Supply Voltage (5.0 V or 3.3 V ±10%)

1. Standard option. Tri-State can be connected to pin 5 and CMOS/TTL select would be on pin 2.

2. Output is HCMOS. For frequencies >12MHz, this option optimizes symmetry for either CMOS or TTL thresholds. Ground this pin

for frequencies < 12MHz.

Table 2. Electrical Performance @ 25°C for the CMOS output option

Parameter

Supply Voltage ¹, +5 volt option

+3.3 volt option

Symbol

Minimum

4.5

Typical Maximum Units

5.0

3.3

5.5

3.6

3.0

Supply Current

10mA + 0.25mA per MHz, typical

Center Frequency, see ordering information

Operating Temperature, see ordering info

Absolute Pull Range over the operating

temperature range, aging and power supply

Vc= 0.5 to 4.5 or 0.3 to 3.0 V

see ordering information for options

Gain Transfer

F_N

T_OP

APR

1.024

77.760

MHz

°C

ppm

0/70, -40/85

±50 to ±100

K_V

Positive

(Frequency vs. Control Voltage)

Output Level High²

V_OH

V_OL

t_R/t_F

SYM

I_L

0.8*Vcc

kHz

Output Level Low²

0.1*Vcc

Output Rise/Fall Time²

Duty Cycle³, see ordering info

Input Leakage

45/55 or 40/60

±1

Control Voltage Modulation Bandwidth

RMS Jitter, 77.760MHz

RMS Jitter, 77.760MHz, 12kHz to 20MHz

Maximum Control Voltage

Maximum Supply Voltage

<0.5

V_DD

Storage Temperature

Soldering Temp./Time

T_S

T_LS

-55

125

240/10

°C

°C/s

1. Power supply bypass is required and a 0.1uF in parallel with a 0.01uF high frequency capacitor is recommended.

2. Figure 1 defines these parameters. Figure 2 illustrates the load used to test devices.

3. Duty cycle is defined as on-time versus period at 1.4 V for TTL, and 2.5 V for CMOS (5volt supply) and at 1.65 V for CMOS (3.3

volt operation)

T_F

T_R

I_DD

650

Ohm

80%

50%

20%

V_DD

.01µF

.1µF

I_C

V_C

On Time

15pF

1.8k

Ohm

Period

Figure 1. Output Waveform

Figure 2. Output Test Conditions (25±5°C)

for 5 volt devices, 15pF cap only for 3.3V.

Vectron International 267 Lowell Rd. Hudson, NH 03051 Tel:1-88-VECTRON-1

e-mail vectron@vectron.com

123 4 5 6 7...10

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与JCLNLATN@50.000MHZ相关器件

型号	品牌	描述	获取价格	数据表
JCLNLATN@51.840MHZ	MICROSEMI	CMOS/TTL Output Clock Oscillator, 1.024MHz Min, 155.52MHz Max, 51.84MHz Nom, HERMETIC SEAL	获取价格
JCLNLATN@52.000MHZ	MICROSEMI	CMOS/TTL Output Clock Oscillator, 1.024MHz Min, 155.52MHz Max, 52MHz Nom, HERMETIC SEALDED	获取价格
JCLNLATN@8.000MHZ	MICROSEMI	CMOS/TTL Output Clock Oscillator, 1.024MHz Min, 155.52MHz Max, 8MHz Nom, HERMETIC SEALDED,	获取价格
JCLNLATN1.024	MICROSEMI	CMOS/TTL Output Clock Oscillator, 1.024MHz Nom, ROHS COMPLIANT, HERMETIC SEALED, J-LEADE,	获取价格
JCLNLATN-1.024MHZ	ETC	Voltage-Controlled Oscillator	获取价格
JCLNLATN-1.544MHZ	ETC	Voltage-Controlled Oscillator	获取价格

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