Datasheet > IXLD02SI

IXLD02SI

更新时间： 2024-01-23 02:02:52

品牌	Logo	应用领域
IXYS		驱动器二极管激光二极管
页数	文件大小	规格书
6页	164K
描述
Differential 2A Ultra Fast Laser Diode Driver

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技术参数
数据手册

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IXLD02SI 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	SOIC-28
针数：	28	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8541.90
风险等级：	5.84	接口集成电路类型：	INTERFACE CIRCUIT
JESD-30 代码：	R-PDSO-G28	长度：	17.9 mm
功能数量：	1	端子数量：	28
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	HSOP
封装等效代码：	SOP28,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	2.65 mm
子类别：	Display Drivers	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	7.5 mm
Base Number Matches：	1

IXLD02SI 数据手册

IXLD02SI

Pin Configurations And Package Outline

NOTE: Bottom-side heat sinking metalization is connected to ground

Pin Description

Pins Nam e

Description

1,2,

This pin is a high current, low inductance pin designed to accept peaks

VDD

13, 14

of 2Amps at 5V.

This is a low current analog power input. Circuit com ponents sensitive

to the noise present on VDD in are supplied by this pin.

VDDA

VTT This pin is the 1/2VDDA internal analog com parator reference point.

Low current, low noise analog return. Noise sensitive circuit

GNDA

components are returned here.

The current, I_IBI, flowing into the IBI pin acts as a baseline current with

IBI

respect to I_IPWcurrent to com pensate for internal delays. See Figure 2.

A current, I_IOP, into the IOP pin program s the laser diode output

IOP switches, pin 19 through pin 24. The program ratio is 1:1000X. This

m eans a 1m A current will produce 1Am p. See Figure 2.

A current, I_IPW, flowing into the IPW pin determ ines the output current

pulse width, t_PW, with respect to I_IBI. If I_IPW=I_IBI, the pulse width is 0. As

IPW

I_IPWapproaches I_IBIbut less than I_IBI, the pulse width becom es non-

zero. See Figure 2 for t_PWas a function of I_IBIand I_IPW

A TTL high on this pin will power down the device so that only leakage

PDN current will flow from VDD to DGND. A TTL low will turn on the device

within 30ns. See Figure 3.

A system reset pin, which initializes the device so that it starts in a

RST

predeterm ined initial state.

This pin is the return for the input logic, I_IBI, I_{IO P}, and I_IPWcurrents. It is

DGND internally connected to the other grounds, AGND or GND, through the

substrate.

W ith PDN low, a positive edge of a TTL compatible signal here will

produce the pulse current output available at the OUT and a

FIN

complem ent of it at OUTb pins. Refer to Figure 3 for FIN and PDN

tim ing.

15, 16,

17, 18,

25, 26,

27, 28

GND Output ground pins designed for low inductance.

19, 20.

True laser diode drive output current. Designed for low inductance and

OUT

output voltage compliance to +12V.

22, 23,

Com plem entary laser diode drive output current. Designed for low

OUTb

inductance and output voltage compliance to +12V.

1 2 345 6

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