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ISPLSI2032-110LJN PDF预览

ISPLSI2032-110LJN

更新时间： 2024-11-15 09:56:27
品牌 Logo 应用领域
莱迪思 - LATTICE 时钟输入元件可编程逻辑
页数 文件大小 规格书
16页 294K
描述
EE PLD, 13ns, CMOS, PQCC44, PLASTIC, LCC-44

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中文翻译

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ISPLSI2032-110LJN 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：LCC
包装说明：QCCJ,针数：44
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.72
其他特性：IN-SYSTEM PROGRAMMABLE; 3 EXTERNAL CLOCKS最大时钟频率：77 MHz
JESD-30 代码：S-PQCC-J44JESD-609代码：e3
长度：16.5862 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：32
端子数量：44最高工作温度：70 °C
最低工作温度：组织：0 DEDICATED INPUTS, 32 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：250
可编程逻辑类型：EE PLD传播延迟：13 ns
认证状态：Not Qualified座面最大高度：4.572 mm
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：16.5862 mm
Base Number Matches：1

ISPLSI2032-110LJN 数据手册

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Lead-  
ee  
Fr  
®
Package  
ispLSI 2032/A  
Options  
vailable!  
A
In-System Programmable High Density PLD  
Features  
Functional Block Diagram  
• ENHANCEMENTS  
— ispLSI 2032A is Fully Form and Function Compatible  
to the ispLSI 2032, with Identical Timing  
Specifcations and Packaging  
— ispLSI 2032A is Built on an Advanced 0.35 Micron  
E2CMOS® Technology  
• HIGH DENSITY PROGRAMMABLE LOGIC  
Global Routing Pool  
A0  
A1  
A2  
A7  
A6  
A5  
A4  
(GRP)  
— 1000 PLD Gates  
— 32 I/O Pins, Two Dedicated Inputs  
— 32 Registers  
— High Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
D
D
D
D
Q
Q
Q
Q
Logic  
Array  
GLB  
A3  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— fmax = 180 MHz Maximum Operating Frequency  
— tpd = 5.0 ns Propagation Delay  
— TTL Compatible Inputs and Outputs  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
0139Bisp/2000  
— 100% Tested at Time of Manufacture  
— Unused Product Term Shutdown Saves Power  
Description  
• IN-SYSTEM PROGRAMMABLE  
The ispLSI 2032 and 2032A are High Density Program-  
mable Logic Devices. The devices contain 32 Registers,  
32 Universal I/O pins, two Dedicated Input Pins, three  
Dedicated Clock Input Pins, one dedicated Global OE  
input pin and a Global Routing Pool (GRP). The GRP  
provides complete interconnectivity between all of these  
elements. The ispLSI 2032 and 2032A feature 5V in-  
system programmability and in-system diagnostic  
capabilities. The ispLSI 2032 and 2032A offer non-  
volatile reprogrammability of the logic, as well as the  
interconnect to provide truly reconfigurable systems.  
— In-System Programmable (ISP™) 5V Only  
— Increased Manufacturing Yields, Reduced Time-to-  
Market and Improved Product Quality  
— Reprogram Soldered Devices for Faster Prototyping  
• OFFERS THE EASE OF USE AND FAST SYSTEM  
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY  
OF FIELD PROGRAMMABLE GATE ARRAYS  
— Complete Programmable Device Can Combine Glue  
Logic and Structured Designs  
— Enhanced Pin Locking Capability  
— Three Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control to  
Minimize Switching Noise  
— Flexible Pin Placement  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
The basic unit of logic on these devices is the Generic  
Logic Block (GLB). The GLBs are labeled A0, A1 .. A7  
(Figure 1). There are a total of eight GLBs in the ispLSI  
2032 and 2032A devices. Each GLB is made up of four  
macrocells. Each GLB has 18 inputs, a programmable  
AND/OR/ExclusiveORarray, andfouroutputswhichcan  
be configured to be either combinatorial or registered.  
Inputs to the GLB come from the GRP and dedicated  
inputs. All of the GLB outputs are brought back into the  
GRP so that they can be connected to the inputs of any  
GLB on the device.  
— Lead-Free Package Options  
Copyright©2006LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
August 2006  
2032_11  
1
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ISPLSI2032-110LT44I LATTICE

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ISPLSI2032-110LTN48 LATTICE

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 		EE PLD, 13ns, CMOS, PQFP48, TQFP-48
ISPLSI2032-135LJ LATTICE

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 		In-System Programmable High Density PLD
ISPLSI2032-135LJ44 LATTICE

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 		EE PLD, 12ns, 32-Cell, CMOS, PQCC44, PLASTIC, LCC-44
ISPLSI2032-135LJI LATTICE

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 		In-System Programmable High Density PLD
ISPLSI2032-135LJN LATTICE

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