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ISPLSI1048E-70LQN PDF预览

ISPLSI1048E-70LQN

更新时间： 2024-11-14 14:21:31
品牌 Logo 应用领域
莱迪思 - LATTICE 时钟输入元件可编程逻辑
页数 文件大小 规格书
17页 275K
描述
EE PLD, 18.5ns, 192-Cell, CMOS, PQFP128, LEAD FREE, PLASTIC, QFP-128

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ISPLSI1048E-70LQN 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：QFP
包装说明：QFP, QFP128,1.2SQ,32针数：128
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.8
Is Samacsys：N其他特性：USE ISPLSI1048EA FOR NEW DESIGNS
最大时钟频率：56 MHz系统内可编程：YES
JESD-30 代码：S-PQFP-G128JESD-609代码：e3
JTAG BST：NO长度：28 mm
湿度敏感等级：3专用输入次数：8
I/O 线路数量：96宏单元数：192
端子数量：128最高工作温度：70 °C
最低工作温度：组织：8 DEDICATED INPUTS, 96 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP128,1.2SQ,32
封装形状：SQUARE封装形式：FLATPACK
峰值回流温度（摄氏度）：225电源：5 V
可编程逻辑类型：EE PLD传播延迟：18.5 ns
认证状态：Not Qualified座面最大高度：4.1 mm
子类别：Programmable Logic Devices最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：28 mmBase Number Matches：1

ISPLSI1048E-70LQN 数据手册

 浏览型号ISPLSI1048E-70LQN的Datasheet PDF文件第2页浏览型号ISPLSI1048E-70LQN的Datasheet PDF文件第3页浏览型号ISPLSI1048E-70LQN的Datasheet PDF文件第4页浏览型号ISPLSI1048E-70LQN的Datasheet PDF文件第5页浏览型号ISPLSI1048E-70LQN的Datasheet PDF文件第6页浏览型号ISPLSI1048E-70LQN的Datasheet PDF文件第7页 
Lead-  
ee  
Fr  
Package  
®
ispLSI 1048E  
Options  
vailable!  
A
In-System Programmable High Density PLD  
Features  
Functional Block Diagram  
• HIGH DENSITY PROGRAMMABLE LOGIC  
— 8,000 PLD Gates  
Output Routing Pool  
Output Routing Pool  
F7 F6 F5 F4 F3 F2 F1 F0  
E7 E6 E5 E4 E3 E2 E1 E0  
— 96 I/O Pins, Twelve Dedicated Inputs  
— 288 Registers  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
D
D
D
D
Q
Q
Q
Q
— High-Speed Global Interconnects  
Logic  
Array  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
Global Routing Pool (GRP)  
GLB  
— Small Logic Block Size for Random Logic  
— Functionally and Pin-out Compatible to ispLSI 1048C  
B0 B1 B2 B3 B4 B5 B6 B7  
Output Routing Pool  
C0 C1 C2 C3 C4 C5 C6 C7  
Output Routing Pool  
CLK  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— fmax = 125 MHz Maximum Operating Frequency  
0139G1A-isp  
— tpd = 7.5 ns Propagation Delay  
— TTL Compatible Inputs and Outputs  
— Electrically Eraseable and Reprogrammable  
— Non-Volatile  
Description  
The ispLSI 1048E is a High Density Programmable Logic  
Device containing 288 Registers, 96 Universal I/O pins,  
12 Dedicated Input pins, four Dedicated Clock Input pins,  
twodedicatedGlobalOEinputpins,andaGlobalRouting  
Pool(GRP).TheGRPprovidescompleteinterconnectivity  
between all of these elements. The ispLSI 1048E offers  
5Vnon-volatilein-systemprogrammabilityofthelogic,as  
well as the interconnect to provide truly reconfigurable  
systems. A functional superset of the ispLSI 1048 archi-  
tecture, the ispLSI 1048E device adds two new global  
output enable pins and two additional dedicated inputs.  
— 100% Tested at Time of Manufacture  
• IN-SYSTEM PROGRAMMABLE  
— In-System Programmable (ISP™) 5V Only  
— Increased Manufacturing Yields, Reduced Time-to-  
Market and Improved Product Quality  
— Reprogram Soldered Devices for Faster Prototyping  
• OFFERS THE EASE OF USE AND FAST SYSTEM  
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY  
OF FIELD PROGRAMMABLE GATE ARRAYS  
The basic unit of logic on the ispLSI 1048E device is the  
Generic Logic Block (GLB). The GLBs are labeled A0,  
A1…F7(seeFigure1). Thereareatotalof48GLBsinthe  
ispLSI 1048E device. Each GLB has 18 inputs, a pro-  
grammableAND/OR/ExclusiveORarray,andfouroutputs  
which can be configured to be either combinatorial or  
registered. Inputs to the GLB come from the GRP and  
dedicated inputs. All of the GLB outputs are brought back  
into the GRP so that they can be connected to the inputs  
of any other GLB on the device.  
— Complete Programmable Device Can Combine Glue  
Logic and Structured Designs  
— Enhanced Pin Locking Capability  
— Four Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control to  
Minimize Switching Noise  
— Flexible Pin Placement  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
— Lead-Free Package Options  
Copyright©2006LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
August 2006  
1048e_12  
1
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