Datasheet > ISPGAL22V10C-7LK

ISPGAL22V10C-7LK

更新时间： 2024-01-20 16:25:32

品牌	Logo	应用领域
其他 - ETC		可编程逻辑器件
页数	文件大小	规格书
14页	221K
描述
Electrically-Erasable PLD

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中文翻译

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数据手册

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ISPGAL22V10C-7LK 数据手册

ispGAL22V10

In-System Programmable E²CMOS PLD

Generic Array Logic™

Features

Functional Block Diagram

• IN-SYSTEM PROGRAMMABLE™ (5-V ONLY)

— 4-Wire Serial Programming Interface

RESET

I/CLK

— Minimum 10,000 Program/Erase Cycles

— Built-in Pull-Down on SDI Pin Eliminates Discrete

Resistor on Board (ispGAL22V10C Only)

OLMC

I/O/Q

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— 7.5 ns Maximum Propagation Delay

— Fmax = 111 MHz

OLMC

I/O/Q

OLMC

I/O/Q

— 5 ns Maximum from Clock Input to Data Output

— UltraMOS^®Advanced CMOS Technology

• ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS

OLMC

I/O/Q

• COMPATIBLE WITH STANDARD 22V10 DEVICES

— Fully Function/Fuse-Map/Parametric Compatible

with Bipolar and CMOS 22V10 Devices

OLMC

I/O/Q

• E²CELL TECHNOLOGY

OLMC

I/O/Q

— In-System Programmable Logic

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

OLMC

I/O/Q

• TEN OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

OLMC

I/O/Q

• APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Software-Driven Hardware Configuration

OLMC

SDO

SDI

MODE

SCLK

PROGRAMMING

LOGIC

PRESET

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

Description

Pin Configuration

The ispGAL22V10, at 7.5ns maximum propagation delay time,

combines a high performance CMOS process with Electrically Eras-

able (E²) floating gate technology to provide the industry's first in-

system programmable 22V10 device. E²technology offers high

speed (<100ms) erase times, providing the ability to reprogram or

reconfigure the device quickly and efficiently.

PLCC

SSOP

Vcc

SCLK

2 5 I/O/Q

I/O/Q

I/CLK

I/O/Q

SDO

I/O/Q

The generic architecture provides maximum design flexibility by al-

lowing the Output Logic Macrocell (OLMC) to be configured by the

user. The ispGAL22V10 is fully function/fuse map/parametric com-

patible with standard bipolar and CMOS 22V10 devices. The stan-

dard PLCC package provides the same functional pinout as the

standard 22V10 PLCC package with No-Connect pins being used

for the ISP interface signals.

ispGAL

22V10

2 3

I/O/Q

ispGAL22V10

Top View

MODE

SDO

MODE

Top View

I/O/Q

1 9 I/O/Q

1 4

1 6

SDI

GND

Unique test circuitry and reprogrammable cells allow completeAC,

DC, and functional testing during manufacture. As a result, Lat-

tice Semiconductor delivers 100% field programmability and func-

tionality of all GAL products. In addition, 10,000 erase/write cycles

and data retention in excess of 20 years are specified.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

July 1997

isp22v10_02

12 3 4 5 6 7...14

中文翻译

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与ISPGAL22V10C-7LK相关器件

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ISPGDS18-7P	LATTICE	获取价格	in-system programmable Generic Digital SwitchTM
ISPGDS22	LATTICE	获取价格	in-system programmable Generic Digital SwitchTM
ISPGDS22-7J	LATTICE	获取价格	in-system programmable Generic Digital SwitchTM
ISPGDS22-7JN	LATTICE	获取价格	暂无描述
ISPGDS22-7P	LATTICE	获取价格	in-system programmable Generic Digital SwitchTM
ISPGDX	LATTICE	获取价格	In-System Programmable Generic Digital Crosspoint
ISPGDX120A-5Q160	LATTICE	获取价格	In-System Programmable Generic Digital CrosspointTM
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