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ISPGDX

更新时间： 2024-02-28 04:43:02

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
23页	229K
描述
In-System Programmable Generic Digital Crosspoint

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ISPGDX 数据手册

ispGDX Family

In-System Programmable

Generic Digital Crosspoint

Features

Functional Block Diagram

• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL

CROSSPOINT FAMILY

ISP

Control

I/O Pins D

— Advanced Architecture Addresses Programmable

PCB Interconnect, Bus Interface Integration and

Jumper/Switch Replacement

— Three Device Options: 80 to 160 Programmable I/O

Pins

— “Any Input to Any Output” Routing

— Fixed HIGH or LOW Output Option for Jumper/DIP

Switch Emulation

— Space-Saving TQFP, PQFP and BGA Packaging

— Dedicated IEEE 1149.1-Compliant Boundary Scan

Test

Global Routing

Pool

I/O

Cells

I/O

Cells

(GRP)

— PCI Compliant Output Drive

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— 5V Power Supply

— 5.0ns Input-to-Output/5.0ns Clock-to-Output Delay

— Low-Power: 40mA Quiescent Icc

— Balanced 24mA Output Buffers with Programmable

Slew Rate Control

— Schmitt Trigger Inputs for Noise Immunity

— Electrically Erasable and Reprogrammable

— Non-Volatile E²CMOS Technology

— 100% Tested

Boundary

Scan

I/O Pins B

Control

Description

• ispGDX OFFERS THE FOLLOWING ADVANTAGES

TheispGDXarchitectureprovidesafamilyoffast,flexible

programmable devices to address a variety of system-

level digital signal routing and interface requirements

including:

— In-System Programmable

— Lattice ISP or JTAG Programming Interface

— Only 5V Power Supply Required

— Change Interconnects in Seconds

— Reprogram Soldered Devices

• Multi-Port Multiprocessor Interfaces

• FLEXIBLE ARCHITECTURE

• Wide Data and Address Bus Multiplexing

(e.g. 4:1 High-Speed Bus MUX)

— Combinatorial/Latched/Registered Inputs or Outputs

— Individual I/O Tri-state Control with Polarity Control

— Dedicated Clock Input Pins (two or four) or

Programmable Clocks from I/O Pins (from 20 up to

40)

• Programmable Control Signal Routing

(e.g. Interrupts, DMAREQs, etc)

— Up to 4:1 Dynamic Path Selection

— Programmable Output Pull-up Resistors

— Outputs Tri-state During Power-up (“Live Insertion”

Friendly)

• Board-Level PCB Signal Routing for Prototyping or

Programmable Bus Interfaces

The ispGDX Family consists of three members with 80,

120 and 160 Programmable I/Os. These devices are

available in packages ranging from the 100-pin TQFP to

the 208-pin PQFP. The devices feature fast operation,

with input-to-output signal delays (Tpd) of 5ns and clock-

to-output delays of 5ns.

The architecture of the devices consists of a series of

programmableI/OcellsinterconnectedbyaGlobalRout-

are subject to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

November 2003

ispgdx_11

12 3 4 5 6 7...23

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与ISPGDX相关器件

型号	品牌	获取价格	描述	数据表
ISPGDX120A-5Q160	LATTICE	获取价格	In-System Programmable Generic Digital CrosspointTM
ISPGDX120A-5T176	LATTICE	获取价格	In-System Programmable Generic Digital CrosspointTM
ISPGDX120A-7Q160	LATTICE	获取价格	In-System Programmable Generic Digital CrosspointTM
ISPGDX120A-7T176	LATTICE	获取价格	In-System Programmable Generic Digital CrosspointTM
ISPGDX160-5B272	LATTICE	获取价格	In-System Programmable Generic Digital CrosspointTM
ISPGDX160-5Q208	LATTICE	获取价格	In-System Programmable Generic Digital CrosspointTM
ISPGDX160-7B272	LATTICE	获取价格	In-System Programmable Generic Digital CrosspointTM
ISPGDX160-7Q208	LATTICE	获取价格	In-System Programmable Generic Digital CrosspointTM
ISPGDX160A-5B272	LATTICE	获取价格	In-System Programmable Generic Digital CrosspointTM
ISPGDX160A-5Q208	LATTICE	获取价格	In-System Programmable Generic Digital CrosspointTM

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