Datasheet > ISPGAL22LV10-15LK

ISPGAL22LV10-15LK

更新时间： 2024-09-29 23:59:51

品牌	Logo	应用领域
其他 - ETC		可编程逻辑器件
页数	文件大小	规格书
14页	254K
描述
Electrically-Erasable PLD

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中文翻译

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数据手册

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ispGAL^®22LV10

In-System Programmable Low Voltage

E²CMOS^®PLD Generic Array Logic™

Features

Functional Block Diagram

• IN-SYSTEM PROGRAMMABLE

— IEEE 1149.1 Standard TAP Controller Port

Programming

RESET

I/CLK

OLMC

I/O/Q

— 4-Wire Serial Programming Interface

— Minimum 10,000 Program/Erase Cycles

OLMC

I/O/Q

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— 4 ns Maximum Propagation Delay

— Fmax = 250 MHz

OLMC

I/O/Q

— 3 ns Maximum from Clock Input to Data Output

— UltraMOS^®Advanced CMOS Technology

• 3.3V LOW VOLTAGE 22V10 ARCHITECTURE

— JEDEC-Compatible 3.3V Interface Standard

— 5V Tolerant Inputs and I/O

OLMC

I/O/Q

— I/O Interfaces with Standard 5V TTL Devices

OLMC

I/O/Q

• ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS

OLMC

• COMPATIBLE WITH STANDARD 22LV10/22V10 DEVICES

— Function/Fuse-Map Compatible with 22LV10/22V10

Devices

I/O/Q

OLMC

I/O/Q

— Parametric Compatible with 22LV10

• E²CELL TECHNOLOGY

— In-System Programmable Logic

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

OLMC

I/O/Q

OLMC

• APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Software-Driven Hardware Configuration

TDO

TDI

TMS

TCK

PROGRAMMING

LOGIC

PRESET

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

Pin Configuration

Description

PLCC

The ispGAL22LV10 is manufactured using Lattice Semiconductor's

advanced 3.3V E²CMOS process, which combines CMOS with

Electrically Erasable (E²) floating gate technology. The

ispGAL22LV10 can interface with both 3.3V and 5V signal levels.

SSOP

Vcc

TCK

I/O/Q

I/CLK

I/O/Q

The ispGAL22LV10 is fully function/fuse map compatible with the

GAL^®22LV10 and GAL22V10. Further, the ispGAL22LV10 is para-

metric compatible with the GAL22LV10. The ispGAL22LV10 also

shares the same 28-pin PLCC package pin-out as the GAL22LV10.

I/O/Q

TDO

I/O/Q

ispGAL

22LV10

ispGAL22LV10

Top View

TMS

TDO

I/O/Q

TMS

Top View

Unique test circuitry and reprogrammable cells allow completeAC,

DC, and functional testing during manufacture. As a result, Lat-

tice Semiconductor delivers 100% field programmability and func-

tionality of all GAL products. In addition, 10,000 erase/write cycles

and data retention in excess of 20 years are specified.

TDI

GND

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com

December 1999

isp22lv_06

12 3 4 5 6 7...14

中文翻译

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与ISPGAL22LV10-15LK相关器件

型号	品牌	获取价格	描述	数据表
ISPGAL22LV10-15LKI	ETC	获取价格	Electrically-Erasable PLD
ISPGAL22LV10-4LJ	ETC	获取价格	Electrically-Erasable PLD
ISPGAL22LV10-4LK	ETC	获取价格	Electrically-Erasable PLD
ISPGAL22LV10-5LJ	ETC	获取价格	Electrically-Erasable PLD
ISPGAL22LV10-5LJI	LATTICE	获取价格	EE PLD, 5ns, CMOS, PQCC28, PLASTIC, LCC-28
ISPGAL22LV10-5LK	ETC	获取价格	Electrically-Erasable PLD
ISPGAL22LV10-5LKI	LATTICE	获取价格	EE PLD, 5ns, CMOS, PDSO28, SSOP-28
ISPGAL22LV10-7LJ	ETC	获取价格	Electrically-Erasable PLD
ISPGAL22LV10-7LJI	ETC	获取价格	Electrically-Erasable PLD
ISPGAL22LV10-7LK	ETC	获取价格	Electrically-Erasable PLD

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