Datasheet > ISPGAL22V10

ISPGAL22V10

更新时间： 2024-01-06 09:06:24

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
15页	247K
描述
In-System Programmable E2CMOS PLD

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中文翻译

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数据手册

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ISPGAL22V10 数据手册

^Specificati^iosⁿp^sG^ispA^GL^A2^L2²²V^V1¹0⁰

In-System Programmable E²CMOS PLD

Generic Array Logic™

FEATURES

FUNCTIONAL BLOCK DIAGRAM

• IN-SYSTEM PROGRAMMABLE™ (5-V ONLY)

— 4-Wire Serial Programming Interface

RESET

I/CLK

— Minimum 10,000 Program/Erase Cycles

— Built-in Pull-Down on SDI Pin Eliminates Discrete

Resistor on Board (ispGAL22V10C Only)

OLMC

I/O/Q

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— 7.5 ns Maximum Propagation Delay

— Fmax = 111 MHz

OLMC

I/O/Q

— 5 ns Maximum from Clock Input to Data Output

OLMC

I/O/Q

— UltraMOS^®Advanced CMOS Technology

• ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS

OLMC

I/O/Q

• COMPATIBLE WITH STANDARD 22V10 DEVICES

— Fully Function/Fuse-Map/Parametric Compatible

with Bipolar and CMOS 22V10 Devices

OLMC

I/O/Q

• E²CELL TECHNOLOGY

— In-System Programmable Logic

— 100% Tested/100% Yields

OLMC

I/O/Q

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

OLMC

I/O/Q

• TEN OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

OLMC

I/O/Q

• APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Software-Driven Hardware Configuration

OLMC

SDO

SDI

MODE

SCLK

PROGRAMMING

LOGIC

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

DESCRIPTION

PRESET

PIN CONFIGURATION

PLCC

The ispGAL22V10, at 7.5ns maximum propagation delay time,

combines a high performance CMOS process with Electrically

Erasable (E²) floating gate technology to provide the industry's

first in-system programmable 22V10 device. E²technology of-

fers high speed (<100ms) erase times, providing the ability to re-

program or reconfigure the device quickly and efficiently.

SSOP

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user. The ispGAL22V10 is fully function/fuse map/parametric

compatible with standard bipolar and CMOS 22V10 devices. The

standard PLCC package provides the same functional pinout as

the standard 22V10 PLCC package with No-Connect pins being

used for the ISP interface signals.

Vcc

SCLK

2 5 I/O/Q

I/O/Q

I/CLK

I/O/Q

SDO

I/O/Q

ispGAL

22V10

2 3

I/O/Q

ispGAL22V10

Top View

MODE

SDO

MODE

Top View

I/O/Q

Unique test circuitry and reprogrammable cells allow complete

AC, DC, and functional testing during manufacture. As a result,

Lattice Semiconductor delivers 100% field programmability and

functionality of all GAL products. In addition, 10,000 erase/write

cycles and data retention in excess of 20 years are specified.

1 9 I/O/Q

1 4

1 6

SDI

GND

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com

July 1997

isp22v10_02

12 3 4 5 6 7...15

中文翻译

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与ISPGAL22V10相关器件

型号	品牌	获取价格	描述	数据表
ISPGAL22V10AB-28LJ	LATTICE	获取价格	EE PLD, 2.8ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28
ISPGAL22V10AB-5LJ	LATTICE	获取价格	EE PLD, 5ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28
ISPGAL22V10AB-5LJN	LATTICE	获取价格	EE PLD, 5ns, CMOS, PQCC28, PLASTIC, LCC-28
ISPGAL22V10AB-5LJNI	LATTICE	获取价格	EE PLD, 5ns, CMOS, PQCC28, PLASTIC, LCC-28
ISPGAL22V10AB-5LS	LATTICE	获取价格	EE PLD, 5ns, PAL-Type, CMOS, 5 X 5 MM, QFN-32
ISPGAL22V10AB-75LSI	LATTICE	获取价格	EE PLD, 7.5ns, PAL-Type, CMOS, 5 X 5 MM, QFN-32
ISPGAL22V10AC-23LS	LATTICE	获取价格	EE PLD, 2.3ns, PAL-Type, CMOS, 5 X 5 MM, QFN-32
ISPGAL22V10AC-28LJ	LATTICE	获取价格	EE PLD, 2.8ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28
ISPGAL22V10AC-5LJ	LATTICE	获取价格	EE PLD, 5ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28
ISPGAL22V10AC-5LJI	LATTICE	获取价格	EE PLD, 5ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28

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