ISO7221C-HT
www.ti.com
SLLSE78 –APRIL 2011
DUAL DIGITAL ISOLATOR
Check for Samples: ISO7221C-HT
1
FEATURES
SUPPORTS EXTREME TEMPERATURE
APPLICATIONS
•
1-, 5- and 25-Mbps Signaling Rate Options
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
–
–
–
Low Channel-to-Channel Output Skew;
1 ns max
Low Pulse-Width Distortion (PWD);
1 ns max
Available in Extreme (–55°C/175°C)
Temperature Range(1)(2)
Low Jitter Content; 1 ns Typ at 150 Mbps
•
4000-Vpeak Isolation, 560 Vpeak VIORM
•
•
•
•
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
–
–
UL 1577 Approved
50-kV/μs Typical Transient Immunity
•
•
•
Operates with 3.3-V or 5-V Supplies
4-kV ESD Protection
Texas Instruments high temperature products
utilize highly optimized silicon (die) solutions
with design and process enhancements to
maximize performance over extended
temperatures.
High Electromagnetic Immunity
APPLICATIONS
ISO7221C
•
•
Down-Hole Drilling
High Temperature Environments
1
2
3
4
8
7
6
5
VCC1
OUTA
INB
VCC2
INA
OUTB
GND2
GND1
(1) Custom temperature ranges available.
(2) Device is qualified to ensure reliable operation for 1000 hours
at maximum rated temperature. This includes, but is not
limited to temperature bake, temperature cycle, electro
migration, bond inter metallic life, and mold compound life.
Such qualification testing should not be viewed as justifying
use of this component beyond specified performance and
environmental limits.
DESCRIPTION
The ISO7221 is a dual-channel digital isolator. To facilitate PCB layout, the channels are oriented in the opposite
directions. This device has a logic input and output buffer separated by TI’s silicon-dioxide (SiO2) isolation
barrier, providing galvanic isolation of up to 4000 V. Used in conjunction with isolated power supplies, this device
blocks high voltage, isolates grounds, and prevents noise currents on a data bus or other circuits from entering
the local ground and interfering with or damaging sensitive circuitry.
A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation
barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or
resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure
the proper dc level of the output. If this dc-refresh pulse is not received every 4 μs, the input is assumed to be
unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.
The small capacitance and resulting time constant provide fast operation with signaling rates available from
0 Mbps (dc) to 150 Mbps.(3) The A-, B- and C-option devices have TTL input thresholds and a noise filter at the
input that prevents transient pulses from being passed to the output of the device. The M-option devices have
CMOS VCC/2 input thresholds and do not have the input noise-filter and the additional propagation delay.
(3) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
5秒后页面跳转
塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
英特尔震撼发布：128核心256线程的至强6性能核处理器
SK海力士量产12层HBM3E，容量高达36GB
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
