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ISO722MD PDF预览

ISO722MD

更新时间: 2024-02-05 13:22:13
品牌 Logo 应用领域
德州仪器 - TI 驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
22页 1372K
描述
3.3-V / 5-V HIGH-SPEED DIGITAL ISOLATORS

ISO722MD 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.31
Is Samacsys:N接口集成电路类型:INTERFACE CIRCUIT
JESD-30 代码:R-PDSO-G8JESD-609代码:e4
长度:4.9 mm湿度敏感等级:1
功能数量:1端子数量:8
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压:5 V
表面贴装:YES温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

ISO722MD 数据手册

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ISO721, ISO721M  
ISO722, ISO722M  
www.ti.com  
SLLS629BJANUARY 2006REVISED MAY 2006  
3.3-V / 5-V HIGH-SPEED DIGITAL ISOLATORS  
FEATURES  
Drop-In Replacement for Most Opto and  
Magnetic Isolators  
4000-V(peak) Isolation  
– UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2)  
IEC 61010-1 and CSA Approved  
APPLICATIONS  
Industrial Fieldbus  
– 50 kV/µs Transient Immunity Typical  
Signaling Rate 0 Mbps to 150 Mbps  
– Low-Propagation Delay  
– Modbus  
– Profibus  
– DeviceNet™ Data Buses  
– Smart Distributed Systems (SDS™)  
Computer Peripheral Interface  
Servo Control Interface  
Data Acquisition  
– Low-Pulse Skew (Pulse-Width Distortion)  
Low-Power Sleep Mode  
High-Electromagnetic Immunity  
Low-Input Current Requirement  
Failsafe Output  
DESCRIPTION  
The ISO721, ISO721M, ISO722, and ISO722M are digital isolators with a logic input and output buffer separated  
by a silicon oxide (SiO2) insulation barrier. This barrier provides galvanic isolation of up to 4000 V. Used in  
conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits  
from entering the local ground, and interfering with or damaging sensitive circuitry.  
A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation  
barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets  
or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to  
ensure the proper dc level of the output. If this dc-refresh pulse is not received for more than 4 µs, the input is  
assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high  
state.  
FUNCTION DIAGRAM  
Isolation Barrier  
DC Channel  
+
_
Filter  
OSC  
+
Pulse Width  
Demodulation  
V
ref  
_
PWM  
+
Carrier Detect  
POR  
BIAS  
POR  
ISO722  
Only  
+
Data MUX  
AC Detect  
3-State  
_
EN  
Input  
+
IN  
V
ref  
_
Filter  
OUT  
Output Buffer  
+
AC Channel  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SDS is a trademark of Honeywell.  
DeviceNet is a trademark of Open Devicenet Vendors Association, Inc.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2006, Texas Instruments Incorporated  

ISO722MD 替代型号

型号 品牌 替代类型 描述 数据表
ISO722MDRG4 TI

完全替代

3.3-V / 5-V HIGH-SPEED DIGITAL ISOLATORS
ISO722MDR TI

完全替代

3.3-V / 5-V HIGH-SPEED DIGITAL ISOLATORS
ISO722DR TI

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