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ISL95811UFUZ-TK PDF预览

ISL95811UFUZ-TK

更新时间： 2024-02-20 13:02:34
品牌 Logo 应用领域
英特矽尔 - INTERSIL 电位器
页数 文件大小 规格书
14页 481K
描述
Single Digitally Controlled Potentiometer (XDCP™)

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ISL95811UFUZ-TK 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：DFN, MSOP包装说明：TSSOP, TSSOP8,.19
针数：8, 8Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.83其他特性：NONVOLATILE MEMORY
标称带宽：1.25 kHz控制接口：2-WIRE SERIAL
转换器类型：DIGITAL POTENTIOMETERJESD-30 代码：S-PDSO-G8
JESD-609代码：e3长度：3 mm
湿度敏感等级：1功能数量：1
位置数：256端子数量：8
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP8,.19封装形状：SQUARE
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：3/5 V认证状态：Not Qualified
电阻定律：LINEAR最大电阻容差：20%
座面最大高度：1.1 mm子类别：Digital Potentiometers
标称供电电压：3.3 V表面贴装：YES
技术：CMOS标称温度系数：45 ppm/ °C
温度等级：AUTOMOTIVE端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
标称总电阻：10000 Ω宽度：3 mm
Base Number Matches：1

ISL95811UFUZ-TK 数据手册

 浏览型号ISL95811UFUZ-TK的Datasheet PDF文件第2页浏览型号ISL95811UFUZ-TK的Datasheet PDF文件第3页浏览型号ISL95811UFUZ-TK的Datasheet PDF文件第4页浏览型号ISL95811UFUZ-TK的Datasheet PDF文件第6页浏览型号ISL95811UFUZ-TK的Datasheet PDF文件第7页浏览型号ISL95811UFUZ-TK的Datasheet PDF文件第8页 
ISL95811  
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)  
MIN  
TYP  
MAX  
SYMBOL  
PARAMETER  
SCL Frequency  
TEST CONDITIONS  
(Note 18) (Note 4) (Note 18) UNITS  
f
400  
50  
kHz  
ns  
SCL  
t
Pulse Width Suppression Time at  
SDA and SCL Inputs  
Any pulse narrower than the max spec is  
suppressed.  
IN  
t
SCL Falling Edge to SDA Output  
Data Valid  
SCL falling edge crossing 30% of V , until  
CC  
900  
ns  
ns  
AA  
SDA exits the 30% to 70% of V  
window.  
CC  
during a STOP  
CC  
t
Time the Bus Must be Free Before SDA crossing 70% of V  
1300  
BUF  
the Start of a New Transmission  
condition, to SDA crossing 70% of V  
the following START condition.  
during  
CC  
t
Clock LOW Time  
Measured at the 30% of V  
Measured at the 70% of V  
crossing.  
crossing.  
1300  
600  
ns  
ns  
ns  
LOW  
CC  
CC  
t
Clock HIGH Time  
HIGH  
t
START Condition Setup Time  
SCL rising edge to SDA falling edge. Both  
crossing 70% of V  
600  
SU:STA  
HD:STA  
SU:DAT  
.
CC  
t
t
START Condition Hold Time  
Input Data Setup Time  
From SDA falling edge crossing 30% of V  
SCL falling edge crossing 70% of V  
to  
to  
600  
100  
ns  
ns  
CC  
.
CC  
From SDA exiting the 30% to 70% of V  
CC  
window, to SCL rising edge crossing 30% of  
V
CC  
t
Input Data Hold Time  
From SCL rising edge crossing 70% of V  
SDA entering the 30% to 70% of V  
0
600  
600  
2
ns  
ns  
ns  
µs  
ns  
HD:DAT  
SU:STO  
HD:STO  
CC  
window.  
CC  
t
STOP Condition Setup Time  
From SCL rising edge crossing 70% of V , to  
SDA rising edge crossing 30% of V  
CC  
.
CC  
STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge. Both  
or Volatile Only Write crossing 70% of V  
STOP Condition Hold Time for Non- From SDA rising edge to SCL falling edge. Both  
t
.
CC  
t
HD:STO:NV  
Volatile Write  
crossing 70% of V  
.
CC  
t
Output Data Hold Time  
From SCL falling edge crossing 30% of V  
,
CC  
0
DH  
until SDA enters the 30% to 70% of V  
window.  
CC  
t
(Note 16)  
(Note 16)  
SDA and SCL Rise Time  
SDA and SCL Fall Time  
From 30% to 70% of V  
20 +  
0.1 * Cb  
250  
250  
400  
ns  
ns  
R
CC  
t
From 70% to 30% of V  
20 +  
0.1 * Cb  
F
CC  
Cb (Note 16)  
Rpu (Note 16)  
Capacitive Loading of SDA or SCL Total on-chip and off-chip  
SDA and SCL Bus Pull-Up Resistor Maximum is determined by t and t .  
10  
1
pF  
kΩ  
R
F
Off-Chip  
For Cb = 400pF, max is about 2kΩ~2.5kΩ.  
For Cb = 40pF, max is about 15kΩ~20kΩ  
t
(Note 17)  
Non-Volatile Write Cycle Time  
WP Setup Time  
12  
20  
ms  
ns  
ns  
WC  
t
Before START condition  
After STOP condition  
600  
600  
SU:WP  
HD:WP  
t
WP Hold Time  
NOTES:  
4. Typical values are for T = +25°C and 3.3V supply voltage.  
A
5. LSB: [V(RW)  
255  
– V(RW) ]/255. V(RW)  
and V(RW) are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the  
255 0  
0
incremental voltage when changing from one tap to an adjacent tap.  
6. ZS error = V(RW) /LSB.  
0
7. FS error = [V(RW)  
255  
– V ]/LSB.  
CC  
8. DNL = [V(RW) – V(RW) ]/LSB-1, for i = 1 to 255. i is the DCP register setting.  
i-1  
i
FN6759.1  
October 6, 2008  
5
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