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ISL8703A

更新时间: 2024-11-17 01:06:07
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瑞萨 - RENESAS /
页数 文件大小 规格书
12页 607K
描述
Adjustable Delay to Subsequent Enable Signal

ISL8703A 数据手册

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DATASHEET  
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A,  
ISL8705A  
FN6381  
Rev 1.00  
July 24, 2014  
The ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A,  
ISL8705A family of ICs provide four delay adjustable  
Features  
• Adjustable Delay to Subsequent Enable Signal  
• Adjustable Delay to Sequence Auto Start  
sequenced outputs while monitoring an input voltage all with  
a minimum of external components.  
High performance DSP, FPGA, µP and various subsystems  
require input power sequencing for proper functionality at  
initial power-up and the ISL870XA provides this function  
while monitoring the distributed voltage for over and  
undervoltage compliance.  
• Adjustable Distributed Voltage Monitoring  
• Under and Overvoltage Adjustable Delay to Auto Start  
Sequence  
• I/O Options  
ENABLE (ISL8700A, ISL8702A, ISL8704A) and  
ENABLE# (ISL8701A, ISL8703A, ISL8705A)  
SEQ_EN (ISL8702A, ISL8703A) and  
SEQ_EN# (ISL8704A, ISL8705A)  
These ICs operate over the +3.3V to +24V nominal voltage  
range. All have a user adjustable time from UV and OV  
voltage compliance to sequencing start via an external  
capacitor when in auto start mode and adjustable time delay  
to subsequent ENABLE output signal via external resistors.  
• Voltage Compliance Fault Output  
• Pb-Free (RoHS Compliant)  
Additionally, the ISL8702A, ISL8703A, ISL8704A and  
ISL8705A provide I/O for sequencing on and off operation  
(SEQ_EN) and for voltage window compliance reporting  
(FAULT) over the +3.3V to +24V nominal voltage range.  
Applications  
• Power Supply Sequencing  
• System Timing Function  
Easily daisy chained for more than 4 sequenced signals.  
Altogether, the ISL870XA provides these adjustable features  
with a minimum of external BOM. See Figure 1 for typical  
implementation.  
Pinout  
ISL870XA  
(14 LD SOIC)  
TOP VIEW  
Ordering Information  
PART NUMBER  
(Note 1)  
PART  
TEMP.  
PACKAGE  
(Pb-free)  
PKG.  
DWG. #  
14  
13  
12  
11  
10  
9
ENABLE_D  
ENABLE_C  
ENABLE_B  
1
2
3
4
5
6
7
VIN  
MARKING RANGE (°C)  
TD  
ISL8700AIBZ*  
ISL8701AIBZ*  
ISL8702AIBZ*  
ISL8703AIBZ*  
ISL8704AIBZ*  
ISL8705AIBZ*  
ISL 8700AIBZ -40 to +85 14 Ld SOIC M14.15  
ISL 8701AIBZ -40 to +85 14 Ld SOIC M14.15  
ISL 8702AIBZ -40 to +85 14 Ld SOIC M14.15  
ISL 8703AIBZ -40 to +85 14 Ld SOIC M14.15  
ISL 8704AIBZ -40 to +85 14 Ld SOIC M14.15  
ISL 8705AIBZ -40 to +85 14 Ld SOIC M14.15  
TC  
ENABLE_A  
OV  
TB  
TIME  
UV  
SEQ_EN (NC on ISL8700A/01A)  
FAULT (NC on ISL8700A/01A)  
GND  
8
ISL8701A, ISL8703A, ISL8705A PINS 1-4 ARE ENABLE# FUNCTION  
ISL8704A, ISL8705A PIN 9 IS SEQ_EN# FUNCTION  
ISL870XAEVAL1 Evaluation Platform  
*Add “-T” suffix for tape and reel.  
NOTES:  
3.3-24V  
1. Intersil Pb-free plus anneal products employ special Pb-free material  
sets; molding compounds/die attach materials and 100% matte tin  
plate termination finish, which are RoHS compliant and compatible  
with both SnPb and Pb-free soldering operations. Intersil Pb-free  
products are MSL classified at Pb-free peak reflow temperatures that  
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.  
EN  
Vo1  
Vo2  
Vo3  
V04  
DC/DC  
VIN  
Ru  
ENABLE_A  
ENABLE_B  
ENABLE_C  
ENABLE_D  
SEQ_EN *  
EN  
DC/DC  
UV  
Rm  
Rl  
FAULT *  
OV  
EN  
EN  
GND TB TC TD TIME  
DC/DC  
DC/DC  
* SEQ_EN and FAULT are not available on ISL8700A and ISL8701A  
FIGURE 1. ISL870XA IMPLEMENTATION  
FN6381 Rev 1.00  
July 24, 2014  
Page 1 of 12  

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