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ISL78302ARNBZ-T7A PDF预览

ISL78302ARNBZ-T7A

更新时间： 2024-11-29 14:51:39
品牌 Logo 应用领域
瑞萨 - RENESAS PC输出元件调节器
页数 文件大小 规格书
13页 791K
描述
Dual LDO with Low Noise, High Performance and Low IQ

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ISL78302ARNBZ-T7A 技术参数

生命周期：Active零件包装代码：DFN
针数：10Reach Compliance Code：compliant
风险等级：2.04Samacsys Confidence：3
Samacsys Status：ReleasedSamacsys PartID：1162822
Samacsys Pin Count：11Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Small Outline No-leadSamacsys Footprint Name：L10.3x3C
Samacsys Released Date：2019-12-26 15:07:49Is Samacsys：N
调节器类型：FIXED POSITIVE MULTIPLE OUTPUT LDO REGULATORBase Number Matches：1

ISL78302ARNBZ-T7A 数据手册

 浏览型号ISL78302ARNBZ-T7A的Datasheet PDF文件第2页浏览型号ISL78302ARNBZ-T7A的Datasheet PDF文件第3页浏览型号ISL78302ARNBZ-T7A的Datasheet PDF文件第4页浏览型号ISL78302ARNBZ-T7A的Datasheet PDF文件第5页浏览型号ISL78302ARNBZ-T7A的Datasheet PDF文件第6页浏览型号ISL78302ARNBZ-T7A的Datasheet PDF文件第7页 
DATASHEET  
ISL78302  
FN7696  
Rev 6.00  
November 6, 2014  
Dual LDO with Low Noise, High Performance and Low IQ  
ISL78302 is a high performance dual LDO capable of sourcing  
300mA current from each output. It has a low standby current  
and is stable with an output capacitance of 1µF to 10µF and  
an ESR of up to 200mΩ.  
Features  
• Integrates two 300mA high performance LDOs  
• Excellent transient response to large current steps  
• ±1.8% Accuracy over all operating conditions  
The device integrates an individual Power-On-Reset (POR)  
function for each output. The POR delay for VO2 can be  
externally programmed by connecting a timing capacitor to the  
CPOR pin. The POR delay for VO1 is internally fixed at  
approximately 2ms. A reference bypass pin is also provided for  
connecting a noise filtering capacitor for low noise and high-  
PSRR applications.  
• Excellent load regulation: <0.1% voltage change across full  
range of load current  
• Extremely low quiescent current: 47µA (both LDOs active)  
• Wide input voltage capability: 2.3V to 6.5V  
• Low dropout voltage: typically 300mV at 300mA  
The quiescent current is typically only 47µA with both LDOs  
enabled and active. Separate enable pins control each  
individual LDO output. When both enable pins are low, the  
device is in shutdown, typically drawing less than 0.5µA.  
• Low output noise: typically 37µV  
at 100µA (1.5V)  
RMS  
• Stable with 1µF to 10µF ceramic capacitors  
• Separate enable and POR pins for each LDO  
• Soft-start and staged turn-on to limit input current surge  
during enable  
The part operates down to 2.3V and up to 6.5V input. The  
typical output voltage can be as low as 1.2V and as high as  
3.3V for each regulator. Please refer to the “Ordering  
Information” on page 3 for standard options.  
• Current limit and over-temperature protection  
• Tiny 10 Lead 3mm x 3mm DFN package  
• AEC-Q100 qualified  
The ISL78302 is AEC-Q100 qualified at the automotive  
temperature range of -40°C to +105°C.  
• Pb-free (RoHS Compliant)  
Applications  
• Radio receivers  
• Camera modules  
• GPS/navigation  
• Infotainment systems  
ISL78302  
10  
9
1
2
VIN (2.3 TO 6.5V)  
ENABLE1  
V
VIN  
VO1  
VO2  
OUT1  
ON  
ON  
EN1  
V
OUT2  
V
OK  
OUT2  
OFF  
ENABLE2  
OFF  
8
7
3
4
EN2  
POR2  
POR1  
RESET2  
(200ms DELAY,  
C3 = 0.01µF)  
V
V
TOO LOW  
OUT2  
V
CBYP  
OK  
OUT1  
6
5
CPOR  
GND  
RESET1  
(2ms DELAY)  
TOO LOW  
C1  
C2  
C3  
C4  
C5  
OUT1  
C1, C4, C5: 1µF X5R CERAMIC CAPACITOR  
C2: 0.01µF X7R CERAMIC CAPACITOR  
C3: 0.01µF X7R CERAMIC CAPACITOR  
FIGURE 1. TYPICAL APPLICATION  
FN7696 Rev 6.00  
November 6, 2014  
Page 1 of 13  
1234567...13

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