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ISL6550CIR PDF预览

ISL6550CIR

更新时间: 2024-11-28 22:57:23
品牌 Logo 应用领域
英特矽尔 - INTERSIL 监控
页数 文件大小 规格书
11页 287K
描述
SAM Supervisor And Monitor

ISL6550CIR 数据手册

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ISL6550A, ISL6550C  
®
January 18, 2005  
FN9036.4  
SAM (Supervisor And Monitor)  
Features  
• 12V supply operation  
The ISL6550 is a precision, flexible, VID-code-controlled  
reference and voltage monitor for high-end microprocessor  
and memory power supplies. It monitors various input  
signals, and supervises the system (typically a DC/DC  
converter) with its output signals. See the Block Diagram for  
reference.  
• 5V reference output  
• 5-bit digital-to-analog converter  
• Programmable DAC Range, within 0.8–5.0V  
• Programmable undervoltage and overvoltage thresholds,  
and latched fault detection  
The ISL6550 includes a 5-bit DAC (Digital-to-Analog  
Converter), which is programmed by the five VID inputs. The  
voltage range of the BDAC (Buffered DAC output) is  
determined by the DACHI and DACLO voltage levels, which  
are externally adjustable through the R1, R2, R3 resistor  
divider network. VREF5 is a precision-trimmed 5V reference,  
and is used to set the voltage at the top of the resistor  
divider.  
• Optional delayed undervoltage (programmable with  
external capacitor)  
• Undervoltage lockout (power-on-reset)  
• Status Indicators (START, PGOOD)  
• Uncommitted operational amplifier  
• Compatible with ISL6551 full bridge controller  
• 20 Lead SOIC and 20 lead QFN (5x5) packages  
• QFN Package:  
- Compliant to JEDEC PUB95 MO-220  
QFN - Quad Flat No Leads - Package Outline  
- Near Chip Scale Package footprint, which improves  
PCB efficiency and has a thinner profile  
Programmable window comparators monitor Overvoltage  
(OV) and Undervoltage (UV) levels. The OVUVSEN input,  
usually coming from the associated power converter device  
is monitored and compared with BDAC; an error band is  
established via the R4 and R5 resistor setting on the  
OVUVTH pin. An optional external capacitor on the UVDLY  
pin gives a programmable delay on the UV. A high gain  
operational amplifier is available at pins VOPP, VOPM, and  
VOPOUT; it can be used as a gain stage to permit  
Applications  
• Power Supplies for High End Microprocessors and Servers  
monitoring voltages that are different from the BDAC levels.  
The PEN (Power supply ENable) input, driven from an open-  
collector source, enables (when logic high) the external  
converter output, via the PGOOD or START outputs (both  
open-drain). They both basically indicate that the power  
supply is enabled (PEN = high) and there are no fault  
conditions. There are two logic options available, which  
determine the START and PGOOD states; see the block  
diagram or the Logic Options Table for more detail. The two  
logic options are identified with a suffix letter A or C in the  
ordering information.  
• Can be paired with the ISL6551 FBC for a complete full-  
bridge 48V-input converter, or used independently  
Ordering Information  
PART  
TEMP. RANGE  
NUMBER  
(°C)  
PACKAGE  
PKG. DWG. #  
ISL6550AIB  
ISL6550CIB  
ISL6550AIR  
ISL6550CIR  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
20 Lead SOIC M20.3  
20 Lead SOIC M20.3  
20 Lead QFN L20.5x5  
20 Lead QFN L20.5x5  
NOTE: The same part numbers with a “-T” suffix are available as  
Tape and Reel.  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright © Intersil Americas Inc. 2001, 2003-2005. All Rights Reserved.  
1
All other trademarks mentioned are the property of their respective owners.  

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