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ISL6545IRZ PDF预览

ISL6545IRZ

更新时间： 2024-01-29 09:15:20
品牌 Logo 应用领域
英特矽尔 - INTERSIL 开关光电二极管输出元件控制器
页数 文件大小 规格书
16页 314K
描述
5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

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ISL6545IRZ 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：DFN, SOIC包装说明：HVSON, SOLCC10,.12,20
针数：10, 8Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.12其他特性：ALSO ADJUSTABLE OUTPUT FROM 0.6 TO 5.5, ALSO OPERATES ON 12V OR 6.5V TO 14.4V SUPPLY
模拟集成电路 - 其他类型：SWITCHING CONTROLLER控制模式：VOLTAGE-MODE
控制技术：PULSE WIDTH MODULATION最大输入电压：5.5 V
最小输入电压：4.5 V标称输入电压：5 V
JESD-30 代码：S-PDSO-N10JESD-609代码：e3
长度：3 mm湿度敏感等级：3
功能数量：1端子数量：10
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HVSON
封装等效代码：SOLCC10,.12,20封装形状：SQUARE
封装形式：SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1 mm
子类别：Switching Regulator or Controllers表面贴装：YES
切换器配置：PUSH-PULL最大切换频率：330 kHz
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn) - annealed
端子形式：NO LEAD端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：3 mmBase Number Matches：1

ISL6545IRZ 数据手册

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www.DataSheet4U.com  
ISL6545, ISL6545A  
hold at T3, the soft-start operation is initiated, and the output  
voltage ramps up between T4 and T5.  
Functional Description  
Initialization (POR and OCP sampling)  
Figure 1 shows a simplified timing diagram. The Power-On-  
Reset (POR) function continually monitors the bias voltage at  
LGATE  
STARTS  
the V pin. Once the rising POR threshold is exceeded  
SWITCHING  
CC  
(V  
POR  
~4V nominal), the POR function initiates the  
COMP/SD (0.25V/DIV)  
Overcurrent Protection (OCP) sample and hold operation  
(while COMP/SD is ~1V). When the sampling is complete,  
V
begins the soft-start ramp.  
OUT  
0.4V  
If the COMP/SD pin is held low during power-up, that will just  
delay the initialization until it is released, and the COMP/SD  
V
LGATE/OCSET (0.25V/DIV)  
OUT  
voltage is above the V  
DISABLE  
trip point.  
(0.5V/DIV)  
GND>  
ND  
3.4ms  
3.4ms  
0 - 3.4ms  
6.8ms  
V
(2V/DIV)  
CC  
T0 T1  
T2  
T3 T4  
T5  
FIGURE 2. LGATE/OCSET AND SOFT-START OPERATION  
Soft-Start and Pre-Biased Outputs  
~4V POR  
Functionally, the soft-start internally ramps the reference on the  
non-inverting terminal of the error amp from zero to 0.6V in a  
nominal 6.8ms The output voltage will thus follow the ramp,  
from zero to final value, in the same 6.8ms (the actual ramp  
V
(1V/DIV)  
OUT  
COMP/SD (1V/DIV)  
seen on the V  
some initialization timing, between T3 and T4).  
will be less than the nominal time, due to  
OUT  
GND>  
ND  
The ramp is created digitally, so there will be 64 small discrete  
steps. There is no simple way to change this ramp rate  
externally, and it is the same for either frequency version of the  
IC (300kHz or 600kHz).  
FIGURE 1. POR AND SOFT-START OPERATION  
Figure 2 shows a typical power-up sequence in more detail.  
The initialization starts at T0, when either V rises above  
CC  
, or the COMP/SD pin is released (after POR). The  
After an initialization period (T3 to T4), the error amplifier  
(COMP/SD pin) is enabled, and begins to regulate the  
converter’s output voltage during soft-start. The oscillator’s  
triangular waveform is compared to the ramping error amplifier  
voltage. This generates PHASE pulses of increasing width that  
charge the output capacitors. When the internally generated  
soft-start voltage exceeds the reference voltage (0.6V), the soft-  
start is complete, and the output should be in regulation at the  
expected voltage. This method provides a rapid and controlled  
output voltage rise; there is no large inrush current charging the  
output capacitors. The entire start-up sequence from POR  
typically takes up to 17ms; up to 10.2ms for the delay and OCP  
sample, and 6.8ms for the soft-start ramp.  
V
POR  
COMP/SD will be pulled up by an internal 20µA current  
source, but the timing will not begin until the COMP/SD  
exceeds the V  
trip point (at T1). The external  
DISABLE  
capacitance of the disabling device, as well as the  
compensation capacitors, will determine how quickly the  
20µA current source will charge the COMP/SD pin. With  
typical values, it should add a small delay compared to the  
soft-start times. The COMP/SD will continue to ramp to ~1V.  
From T1, there is a nominal 6.8ms delay, which allows the V  
pin to exceed 6.5V (if rising up towards 12V), so that the  
internal bias regulator can turn on cleanly. At the same time, the  
LGATE/OCSET pin is initialized, by disabling the LGATE driver  
CC  
Figure 3 shows the normal curve in blue; initialization begins  
at T0, and the output ramps between T1 and T2. If the output  
is pre-biased to a voltage less than the expected value, as  
shown by the magenta curve, the ISL6545 will detect that  
condition. Neither MOSFET will turn on until the soft-start  
and drawing I  
(nominal 21.5μA) through R . This  
OCSET  
OCSET  
sets up a voltage that will represent the OCSET trip point. At  
T2, there is a variable time period for the OCP sample and hold  
operation (0 to 3.4ms nominal; the longer time occurs with the  
higher overcurrent setting). The sample and hold uses a digital  
counter and DAC to save the voltage, so the stored value does  
ramp voltage exceeds the output; V  
starts seamlessly  
OUT  
ramping from there. If the output is pre-biased to a voltage  
above the expected value, as in the red curve, neither  
MOSFET will turn on until the end of the soft-start, at which  
time it will pull the output voltage down to the final value. Any  
not degrade, for as long as the V  
is above V . See the  
CC  
POR  
Overcurrent Protection on page 7 for more details on the  
equations and variables. Upon the completion of sample and  
FN6305.3  
November 15, 2006  
6
1...3456789...16

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