5秒后页面跳转
捷配首页

Datasheet > ISL6545IRZ
ISL6545IRZ PDF预览

ISL6545IRZ

更新时间： 2024-01-29 06:50:40
品牌 Logo 应用领域
英特矽尔 - INTERSIL 开关光电二极管输出元件控制器
页数 文件大小 规格书
16页 314K
描述
5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

阅读下载

中文翻译

获取价格

ISL6545IRZ 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：DFN, SOIC包装说明：HVSON, SOLCC10,.12,20
针数：10, 8Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.12其他特性：ALSO ADJUSTABLE OUTPUT FROM 0.6 TO 5.5, ALSO OPERATES ON 12V OR 6.5V TO 14.4V SUPPLY
模拟集成电路 - 其他类型：SWITCHING CONTROLLER控制模式：VOLTAGE-MODE
控制技术：PULSE WIDTH MODULATION最大输入电压：5.5 V
最小输入电压：4.5 V标称输入电压：5 V
JESD-30 代码：S-PDSO-N10JESD-609代码：e3
长度：3 mm湿度敏感等级：3
功能数量：1端子数量：10
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HVSON
封装等效代码：SOLCC10,.12,20封装形状：SQUARE
封装形式：SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1 mm
子类别：Switching Regulator or Controllers表面贴装：YES
切换器配置：PUSH-PULL最大切换频率：330 kHz
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn) - annealed
端子形式：NO LEAD端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：3 mmBase Number Matches：1

ISL6545IRZ 数据手册

 浏览型号ISL6545IRZ的Datasheet PDF文件第2页浏览型号ISL6545IRZ的Datasheet PDF文件第3页浏览型号ISL6545IRZ的Datasheet PDF文件第4页浏览型号ISL6545IRZ的Datasheet PDF文件第6页浏览型号ISL6545IRZ的Datasheet PDF文件第7页浏览型号ISL6545IRZ的Datasheet PDF文件第8页 
www.DataSheet4U.com  
ISL6545, ISL6545A  
Electrical Specifications Test Conditions: V = 12V, T = 0 to 85°C, Unless Otherwise Noted. (Continued)  
CC  
J
PARAMETER  
Lower Gate Sink Impedance  
Upper Gate Source Impedance  
Upper Gate Sink Impedance  
Lower Gate Source Impedance  
Lower Gate Sink Impedance  
PROTECTION/DISABLE  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
2.0  
MAX  
UNITS  
R
V
= 14.5V; I = 50mA  
= 4.25V; I = 50mA  
= 4.25V; I = 50mA  
= 4.25V; I = 50mA  
= 4.25V; I = 50mA  
-
-
-
-
-
-
-
-
-
-
Ω
Ω
Ω
Ω
Ω
LG-SNKh  
CC  
CC  
CC  
CC  
CC  
R
R
V
V
V
V
3.5  
UG-SRCl  
2.7  
UG-SNKl  
R
R
2.75  
2.1  
LG-SRCl  
LG-SNKl  
OCSET Current Source  
I
ISL6545C; LGATE/OCSET = 0V  
ISL6545I; LGATE/OCSET = 0V  
19.5  
18.0  
21.5  
21.5  
23.5  
23.5  
μA  
μA  
V
OCSET  
Disable Threshold (COMP/SD pin)  
V
0.375  
0.400  
0.425  
DISABLE  
COMP/SD (SOIC Pin 7, DFN Pin 9)  
Functional Pin Description (SOIC,DFN)  
This is a multiplexed pin. During soft-start and normal converter  
operation, this pin represents the output of the error amplifier.  
Use COMP/SD, in combination with the FB pin, to compensate  
the voltage-control feedback loop of the converter.  
VCC (SOIC Pin 5, DFN Pin 6)  
This pin provides the bias supply for the ISL6545, as well as  
the lower MOSFET’s gate, and the BOOT voltage for the  
upper MOSFET’s gate. An internal 5V regulator will supply  
Pulling COMP/SD low (V  
= 0.4V nominal) will  
bias if V  
rises above 6.5V (but the LGATE/OCSET and  
DISABLE  
CC  
shut-down (disable) the controller, which causes the  
oscillator to stop, the LGATE and UGATE outputs to be held  
low, and the soft-start circuitry to re-arm. The external pull-  
down device will initially need to overcome up to 5mA of  
COMP/SD output current. However, once the IC is disabled,  
the COMP output will also be disabled, so only a 20µA  
current source will continue to draw current.  
BOOT will still be sourced by VCC). Connect a well-  
decoupled 5V or 12V supply to this pin.  
FB (SOIC Pin 6, DFN Pin 8)  
This pin is the inverting input of the internal error amplifier. Use  
FB, in combination with the COMP/SD pin, to compensate the  
voltage-control feedback loop of the converter. A resistor divider  
from the output to GND is used to set the regulation voltage.  
When the pull-down device is released, the COMP/SD pin  
will start to rise, at a rate determined by the 20µA charging  
up the capacitance on the COMP/SD pin. When the  
GND (SOIC Pin 3, DFN Pin 4)  
This pin represents the signal and power ground for the IC.  
Tie this pin to the ground island/plane through the lowest  
impedance connection available. For the DFN package, Pin  
4 MUST be connected for electrical GND; the metal pad  
under the package should also be connected to the GND  
plane for thermal conductivity.  
COMP/SD pin rises above the V  
trip point, the  
DISABLE  
ISL6545 will begin a new Initialization and soft-start cycle.  
LGATE/OCSET (SOIC Pin 4, DFN Pin 5)  
Connect this pin to the gate of the lower MOSFET; it provides  
the PWM-controlled gate drive (from V ). This pin is also  
CC  
PHASE (SOIC Pin 8, DFN Pin 10)  
monitored by the adaptive shoot-through protection circuitry to  
determine when the lower MOSFET has turned off.  
Connect this pin to the source of the upper MOSFET, and  
the drain of the lower MOSFET. It is used as the sink for the  
UGATE driver, and to monitor the voltage drop across the  
lower MOSFET for overcurrent protection. This pin is also  
monitored by the adaptive shoot-through protection circuitry  
to determine when the upper MOSFET has turned off.  
During a short period of time following Power-On Reset  
(POR) or shut-down release, this pin is also used to  
determine the overcurrent threshold of the converter.  
Connect a resistor (R  
) from this pin to GND. See the  
OCSET  
Overcurrent Protection section for equations. An  
overcurrent trip cycles the soft-start function, after two  
dummy soft-start time-outs. Some of the text describing the  
LGATE function may leave off the OCSET part of the name,  
when it is not relevant to the discussion.  
UGATE (SOIC Pin 2, DFN Pin 2)  
Connect this pin to the gate of upper MOSFET; it provides  
the PWM-controlled gate drive. It is also monitored by the  
adaptive shoot-through protection circuitry to determine  
when the upper MOSFET has turned off.  
N/C (DFN only; Pin 3, Pin 7)  
BOOT (SOIC Pin 1, DFN Pin 1)  
These two pins in the DFN package are No Connect.  
This pin provides ground referenced bias voltage to the upper  
MOSFET driver. A bootstrap circuit is used to create a voltage  
suitable to drive an N-channel MOSFET (equal to V minus  
CC  
the on-chip BOOT diode voltage drop), with respect to PHASE.  
FN6305.3  
November 15, 2006  
5
12345678...16

中文翻译

下载PDF

ISL6545IRZ 替代型号

型号 品牌 替代类型 描述 数据表
ISL6545CRZ INTERSIL

完全替代

 5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

与ISL6545IRZ相关器件

型号 品牌 获取价格 描述 数据表
ISL6545IRZ-T RENESAS

获取价格

 		5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller; DFN10, SOIC8; T
ISL6548 INTERSIL

获取价格

 		ACPI Regulator/Controller for Dual Channel DDR Memory Systems
ISL6548_06 INTERSIL

获取价格

 		ACPI Regulator/Controller for Dual Channel DDR Memory Systems
ISL6548A INTERSIL

获取价格

 		ACPI Regulator/Controller for Dual Channel DDR Memory Systems
ISL6548A_06 INTERSIL

获取价格

 		ACPI Regulator/Controller for Dual Channel DDR Memory Systems
ISL6548ACRZ INTERSIL

获取价格

 		ACPI Regulator/Controller for Dual Channel DDR Memory Systems
ISL6548ACRZA INTERSIL

获取价格

 		ACPI Regulator/Controller for Dual Channel DDR Memory Systems
ISL6548ACRZA-T INTERSIL

获取价格

 		ACPI Regulator/Controller for Dual Channel DDR Memory Systems
ISL6548ACRZ-T INTERSIL

获取价格

 		ACPI Regulator/Controller for Dual Channel DDR Memory Systems
ISL6548CRZ INTERSIL

获取价格

 		ACPI Regulator/Controller for Dual Channel DDR Memory Systems

与ISL6545IRZ相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证