ISL6545, ISL6545A
ISL6545, ISL6545A
The overcurrent function will trip at a peak inductor current
(I
I
determined by Equation 1:
PEAK)
2 I
xR
OCSET
OCSET
r
= ----------------------------------------------------------
PEAK
(EQ. 1)
DSON
INTERNAL SOFT-START RAMP
where I
is the internal OCSET current source (21.5µA
OCSET
typical). The scale factor of 2 doubles the trip point of the
MOSFET voltage drop, compared to the setting on the
VOUT
(0.5V/DIV)
R
resistor. The OC trip point varies in a system mainly
OCSET
due to the MOSFET’s r
variations (over process,
DS(ON)
current and temperature). To avoid overcurrent tripping in
the normal operating load range, find the R
from Equation 1 with:
resistor
OCSET
GND>
6.8ms
6.8ms
0ms to 6.8ms
6.8ms
1. The maximum r
temperature.
at the highest junction
DS(ON)
t0
t1
t2
t0
t1
FIGURE 5. OVERCURRENT RETRY OPERATION
2. The minimum I
from the specification table.
OCSET
I
----------
+
OUTMAX
I
> I
3. Determine I
for
PEAK
PEAK
Figure 5 shows the output response during a retry of an
output shorted to GND. At time t0, the output has been
2
whereI is the output inductor ripple current.
For an equation for the ripple current see “Output Inductor
Selection” on page 12.
turned off, due to sensing an overcurrent condition. There
are two internal soft-start delay cycles (t1 and t2) to allow the
MOSFETs to cool down, to keep the average power
The range of allowable voltages detected
dissipation in retry at an acceptable level. At time t2, the
output starts a normal soft-start cycle, and the output tries to
ramp. If the short is still applied, and the current reaches the
OCSET trip point any time during soft-start ramp period, the
output will shut off, and return to time t0 for another delay
cycle. The retry period is thus two dummy soft-start cycles
plus one variable one (which depends on how long it takes to
trip the sensor each time). Figure 5 shows an example
where the output gets about half-way up before shutting
down; therefore, the retry (or hiccup) time will be around
17ms. The minimum should be nominally 13.6ms and the
maximum 20.4ms. If the short condition is finally removed,
the output should ramp up normally on the next t2 cycle.
(2*I
*R ) is 0mV to 475mV; but the practical
OCSET OCSET
range for typical MOSFETs is typically in the 20mV to 120mV
ballpark (500 to 3000). If the voltage drop across
R
is set too low, that can cause almost continuous
OCSET
OCP tripping and retry. It would also be very sensitive to
system noise and inrush current spikes, so it should be
avoided. The maximum usable setting is around 0.2V across
R
(0.4V across the MOSFET); values above that
OCSET
might disable the protection. Any voltage drop across
that is greater than 0.3V (0.6V MOSFET trip point)
R
OCSET
will disable the OCP. The preferred method to disable OCP
is simply to remove the resistor; that will be detected that as
no OCP.
Starting up into a shorted load looks the same as a retry into
that same shorted load. In both cases, OCP is always
enabled during soft-start; once it trips, it will go into retry
(hiccup) mode. The retry cycle will always have two dummy
time-outs, plus whatever fraction of the real soft-start time
passes before the detection and shutoff; at that point, the
logic immediately starts a new two dummy cycle time-out.
Note that conditions during power-up or during a retry may
look different than normal operation. During power-up in a
12V system, the IC starts operation just above 4V; if the
supply ramp is slow, the soft-start ramp might be over well
before 12V is reached. So with lower gate drive voltages, the
r
of the MOSFETs will be higher during power-up,
DS(ON)
effectively lowering the OCP trip. In addition, the ripple
current will likely be different at lower input voltage.
Output Voltage Selection
The output voltage can be programmed to any level between
Another factor is the digital nature of the soft-start ramp. On
each discrete voltage step, there is in effect a small load
transient, and a current spike to charge the output
the 0.6V internal reference, up to the V supply. The
IN
ISL6545x can run at near 100% duty cycle at zero load, but
the r
of the upper MOSFET will effectively limit it to
capacitors. The height of the current spike is not controlled; it
is affected by the step size of the output, the value of the
output capacitors, as well as the IC error amp compensation.
So it is possible to trip the overcurrent with in-rush current, in
addition to the normal load and ripple considerations.
DS(ON)
something less as the load current increases. In addition, the
OCP (if enabled) will also limit the maximum effective duty
cycle.
An external resistor divider is used to scale the output
voltage relative to the internal reference voltage, and feed it
back to the inverting input of the error amp. See “Typical
FN6305 Rev 7.00
October 7, 2015
Page 8 of 17
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