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ISL6545 PDF预览

ISL6545

更新时间: 2023-12-20 18:44:10
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瑞萨 - RENESAS /
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17页 834K
描述
5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

ISL6545 数据手册

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ISL6545, ISL6545A  
ISL6545, ISL6545A  
soft-start operation is initiated, and the output voltage ramps  
up between t4 and t5.  
Functional Description  
Initialization (POR and OCP Sampling)  
Figure 1 shows a simplified timing diagram. The  
LGATE  
STARTS  
SWITCHING  
Power-On-Reset (POR) function continually monitors the  
bias voltage at the VCC pin. Once the rising POR threshold  
is exceeded (VPOR ~4V nominal), the POR function initiates  
the Overcurrent Protection (OCP) sample and hold  
operation (while COMP/SD is ~1V). When the sampling is  
complete, VOUT begins the soft-start ramp.  
COMP/SD (0.25V/DIV)  
0.4V  
If the COMP/SD pin is held low during power-up, that will just  
delay the initialization until it is released, and the COMP/SD  
V
LGATE/OCSET (0.25V/DIV)  
OUT  
voltage is above the V  
trip point.  
DISABLE  
(0.5V/DIV)  
GND>  
3.4ms  
3.4ms  
0 - 3.4ms  
6.8ms  
V
(2V/DIV)  
CC  
t0 t1  
t2  
t3 t4  
t5  
FIGURE 2. LGATE/OCSET AND SOFT-START OPERATION  
Soft-Start and Pre-Biased Outputs  
~4V POR  
Functionally, the soft-start internally ramps the reference on  
the non-inverting terminal of the error amp from 0V to 0.6V in  
a nominal 6.8ms The output voltage will thus follow the  
ramp, from zero to final value, in the same 6.8ms (the actual  
V
(1V/DIV)  
OUT  
COMP/SD (1V/DIV)  
ramp seen on the V  
due to some initialization timing, between t3 and t4).  
will be less than the nominal time,  
OUT  
GND>  
The ramp is created digitally, so there will be 64 small  
discrete steps. There is no simple way to change this ramp  
rate externally, and it is the same for either frequency  
version of the IC (300kHz or 600kHz).  
FIGURE 1. POR AND SOFT-START OPERATION  
Figure 2 shows a typical power-up sequence in more detail.  
The initialization starts at T0, when either V rises above  
CC  
, or the COMP/SD pin is released (after POR). The  
After an initialization period (t3 to t4), the error amplifier  
(COMP/SD pin) is enabled, and begins to regulate the  
converter’s output voltage during soft-start. The oscillator’s  
triangular waveform is compared to the ramping error  
amplifier voltage. This generates PHASE pulses of  
increasing width that charge the output capacitors. When the  
internally generated soft-start voltage exceeds the reference  
voltage (0.6V), the soft-start is complete, and the output  
should be in regulation at the expected voltage. This method  
provides a rapid and controlled output voltage rise; there is  
no large inrush current charging the output capacitors. The  
entire start-up sequence from POR typically takes up to  
17ms; up to 10.2ms for the delay and OCP sample, and  
6.8ms for the soft-start ramp.  
V
POR  
COMP/SD will be pulled up by an internal 20µA current  
source, but the timing will not begin until the COMP/SD  
exceeds the V  
trip point (at t1). The external  
DISABLE  
capacitance of the disabling device, as well as the  
compensation capacitors, will determine how quickly the  
20µA current source will charge the COMP/SD pin. With  
typical values, it should add a small delay compared to the  
soft-start times. The COMP/SD will continue to ramp to ~1V.  
From t1, there is a nominal 6.8ms delay, which allows the  
V
pin to exceed 6.5V (if rising up towards 12V), so that  
the internal bias regulator can turn on cleanly. At the same  
time, the LGATE/OCSET pin is initialized, by disabling the  
CC  
LGATE driver and drawing I  
(nominal 21.5µA)  
OCSET  
. This sets up a voltage that will represent  
Figure 3 shows the normal curve in blue; initialization begins  
at t0, and the output ramps between t1 and t2. If the output is  
pre-biased to a voltage less than the expected value, as  
shown by the magenta curve, the ISL6545x will detect that  
condition. Neither MOSFET will turn on until the soft-start  
through R  
OCSET  
the OCSET trip point. At t2, there is a variable time period for  
the OCP sample and hold operation (0ms to 3.4ms nominal;  
the longer time occurs with the higher overcurrent setting).  
The sample and hold uses a digital counter and DAC to save  
the voltage, so the stored value does not degrade, for as  
ramp voltage exceeds the output; V  
starts seamlessly  
OUT  
ramping from there. If the output is pre-biased to a voltage  
above the expected value, as in the red curve, neither  
MOSFET will turn on until the end of the soft-start, at which  
long as the V  
is above V . See “Overcurrent Protection  
CC  
POR  
(OCP)” on page 7 for more details on the equations and  
variables. Upon the completion of sample and hold at t3, the  
FN6305 Rev 7.00  
October 7, 2015  
Page 6 of 17  

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