ISL6524A
®
Data Sheet
April 8, 2005
FN9064.1
VRM8.5 PWM and Triple Linear Power
System Controller
Features
• Provides 4 Regulated Voltages
- Microprocessor Core, AGTL+ Bus, AGP Bus Power,
and North/South Bridge Core
• Drives N-Channel MOSFETs
• Linear Regulator Drives Compatible with both MOSFET
and Bipolar Series Pass Transistors
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast PWM Converter Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio
The ISL6524A provides the power control and protection for
four output voltages in high-performance microprocessor and
computer applications. The IC integrates one PWM controller
and three linear controllers, as well as the monitoring and
protection functions into a 28-pin SOIC package. The PWM
controller regulates the microprocessor core voltage with a
synchronous-rectified buck converter. One linear controller
supplies the computer system’s AGTL+ 1.2V bus power. The
other two linear controllers regulate power for the 1.5V AGP
bus and the 1.8V power for the chipset core voltage and/or
cache memory circuits.
• Excellent Output Voltage Regulation
- Core PWM Output: ±1% Over Temperature
- All Other Outputs: ±3% Over Temperature
• VRM8.5 TTL-Compatible 5-Bit DAC Microprocessor Core
Output Voltage Selection
- Wide Range - 1.050V to 1.825V
• Power-Good Output Voltage Monitors
- Separate delayed VTT Power Good
The ISL6524A includes an Intel VRM8.5 compatible, TTL
5-input digital-to-analog converter (DAC) that adjusts the
microprocessor core-targeted PWM output voltage from
1.050V to 1.825V in 25mV steps. The precision reference and
voltage-mode control provide ±1% static regulation. The linear
regulators use external N-channel MOSFETs or bipolar NPN
pass transistors to provide fixed output voltages of 1.2V ±3%
(V
), 1.5V ±3% (V
) and 1.8V ±3% (V ).
OUT2
OUT3
OUT4
The ISL6524A monitors all the output voltages. A delayed-
rising VTT (V output) Power Good signal is issued
• Over-Voltage and Over-Current Fault Monitors
- Switching Regulator Doesn’t Require Extra Current
OUT2
before the core PWM starts to ramp up. Another system
Power Good signal is issued when the core is within ±10% of
the DAC setting and all other outputs are above their under-
voltage levels. Additional built-in over-voltage protection for
the core output uses the lower MOSFET to prevent output
voltages above 115% of the DAC setting. The PWM
Sensing Element, Uses MOSFET’s r
DS(ON)
• Small Converter Size
- Constant Frequency Operation
- 200kHz Internal Oscillator
• Pb-Free Available (RoHS Compliant)
controllers’ over-current function monitors the output current
by using the voltage drop across the upper MOSFET’s
DS(ON)
Applications
r
, eliminating the need for a current sensing resistor.
•
Motherboard Power Regulation for Computers
Pinout
Ordering Information
ISL6524A (SOIC) TOP VIEW
TEMP.
PKG.
DWG.
#
DRIVE2
1
2
3
4
5
6
7
8
9
28 VCC
RANGE
PART NUMBER
ISL6524ACB*
ISL6524ACBZ* (Note)
ISL6524ACBZA-T (Note) 0 to 70 28 Ld SOIC (Pb-free) M28.3
ISL6524EVAL1 Evaluation Board
(°C)
PACKAGE
FIX
VID3
27 UGATE
26 PHASE
25 LGATE
24 PGND
23 OCSET
22 VSEN1
21 FB
0 to 70 28 Ld SOIC
M28.3
VID2
0 to 70 28 Ld SOIC (Pb-free) M28.3
VID1
VID0
VID25
PGOOD
VTTPG
*Add “-T” suffix for tape and reel.
20 COMP
19 VSEN3
18 DRIVE3
17 GND
FAULT/RT 10
VSEN2 11
SS24 12
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
SS13 13
16 VAUX
15 DRIVE4
VSEN4 14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.