ISL6146
Electrical Specifications
V
= BIAS = 12V, unless otherwise stated. T = +25°C to +85°C. Boldface limits apply over the operating
A
CC
temperature range, -40°C to +125°C. (Continued)
MIN
MAX
SYMBOL
PARAMETERS
Slow Turn-off Time
TEST CONDITIONS
= 12V, V = 18V to 10V,
(Note 8)
TYP
58
(Note 8)
UNITS
µs
t
V
C
= V
80
toffs
IN
BIAS
= 57nF
GATE
GATE
BIAS = 12V, VG = 0V
BIAS = 12V, VG = 20V
I
Turn-On Current
1
mA
mA
mV
ON
0.15
440
V
V
GATE to V Rising Fault Voltage
IN
GATE > V , enabled, FLT output is high.
IN
(Does not apply to ISL6146D and ISL6146E)
320
140
560
300
VG_FLTr
GATE to V Falling Fault Voltage
IN
GATE > V , enabled, FLT output is low.
IN
220
mV
VG_FLTf
(Does not apply to ISL6146D and ISL6146E)
CONTROL AND REGULATION I/O
Reverse Voltage Detection
V
V
rising
35
10
57
30
10
19
79
51
mV
mV
µs
Rr
OUT
Rising V Threshold
OUT
Reverse Voltage Detection
Falling V Threshold
V
V
falling
Rf
OUT
OUT
t
Reverse Voltage Detection Response
Time
Rs
V
Amplifier Forward Voltage Regulation
ISL6146 controls voltage across FET V to
DS
11
28
mV
FWD_VR
V
during static forward operation at loads
FWD_VR
resulting in Id*r
< V
DS(ON)
FWD_VR
V
HS Comparator Input Offset Voltage
ADJ Adjust Threshold with 5k to GND
ADJ Adjust Threshold with 100k to GND
HS Comparator Response Time
-14
0.57
10
0.7
0.8
40
14
1.1
95
mV
V
OS_HS
V
R
R
= 5kΩ to GND
TH(HS5k)
ADJ
ADJ
OUT
V
= 100kΩ to GND
> V , 1ns transition, 5V differential
mV
ns
TH(HS100k)
t
V
V
V
170
450
44
HSpd
IN
V
V
V
to V
to V
Forward Fault Voltage
Forward Fault Voltage
> V , GATE is fully on, FLT output is low
OUT
330
570
mV
mV
FWD_FLT
IN
OUT
IN
IN
V
> V , GATE is fully on, FLT output is high
OUT
FWD_FLT_HYS
IN
OUT
Hysteresis
FAULT OUTPUT
I
FAULT Sink Current
BIAS = 18V FAULT = 0.5V, V < V , V
IN OUT GATE
= V
GL
5
9
mA
µA
µs
FLT_SINK
I
FAULT Leakage Current
FAULT Low to High Delay
FAULT High to Low Delay
FAULT = “V
”, V > V , V
= V + V
0.04
10
10
23
3
FLT_LEAK
FLT_H IN OUT GATE IN GQP
t
GATE = V
to FAULT output is high
FLT_L2H
GQP
t
GATE = V to FAULT output is low
1.7
µs
FLT_H2L
IN
ENABLE UVLO/OVP/ADJ INPUTS
VthRa
VthR_hysa
VthFb
ISL6146A/D EN Rising Vth
580
580
580
580
606
-90
606
+90
606
+90
606
-90
10
631
631
631
631
mV
mV
mV
mV
mV
mV
mV
mV
µs
ISL6146A/D EN Vth Hysteresis
ISL6146B/E EN Falling Vth
VthF_hysb
VthFc
ISL6146B/E EN Vth Hysteresis
ISL6146C OVP Falling Vth
VthF_hysc
VthRc
ISL6146C OVP Vth Hysteresis
ISL6146C UVLO Rising Vth
VthR_hysc
ISL6146C UVLO Vth Hysteresis
EN/UVLO Rising to GATE Rising Delay
EN/OVP Falling to GATE Rising Delay
t
12
12
EN2GTER
9
µs
FN7667.4
April 26, 2013
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