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ISL59921IRZ-T7 PDF预览

ISL59921IRZ-T7

更新时间: 2024-11-19 21:19:43
品牌 Logo 应用领域
瑞萨 - RENESAS 商用集成电路
页数 文件大小 规格书
18页 1140K
描述
Triple Analog Video Delay Lines; QFN20; Temp Range: -40° to 85°C

ISL59921IRZ-T7 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:VQCCN,
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.37
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:S-PQCC-N20
JESD-609代码:e3长度:5 mm
湿度敏感等级:3功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:VQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, VERY THIN PROFILE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:NO LEAD
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5 mm
Base Number Matches:1

ISL59921IRZ-T7 数据手册

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DATASHEET  
ISL59920, ISL59921, ISL59922, ISL59923  
Triple Analog Video Delay Lines  
FN6826  
Rev 4.00  
August 27, 2015  
The ISL59920, ISL59921, ISL59922, and ISL59923 are triple  
analog delay lines that provide skew compensation between  
three high-speed signals. These parts are ideal for  
compensating for the skew introduced by a typical CAT-5,  
CAT-6 or CAT-7 cable (with differing electrical lengths on each  
twisted pair) when transmitting analog video.  
Features  
• 30, 31, 46.5, or 62ns Total delay  
• 1.0, 1.5, or 2.0ns Delay step increments  
• Very low offset voltage  
• Drop-in compatible with the EL9115  
• Low power consumption  
Using a simple serial interface, the ISL59920, ISL59921,  
ISL59922, and ISL59923’s delays are programmable in steps  
of 2, 1.5, 1, or 2ns (respectively) for up to a total delay of 62,  
46.5, 31, or 30ns (respectively) on each channel. The gain of  
the video amplifiers can be set to x1 (0dB) or x2 (6dB) for  
back-termination. The delay lines require a ±5V supply.  
• 20 Ld QFN package  
• Pb-Free (RoHS compliant)  
Applications  
• Skew control for RGB video signals  
• Generating programmable high-speed analog delays  
1
19  
17  
18  
16  
CENABLE  
7
R
2
IN  
+
DELAY LINE  
R
OUT 15  
+
G
B
4
6
IN  
+
+
DELAY LINE  
DELAY LINE  
G
B
13  
11  
OUT  
OUT  
+
+
IN  
X2 20  
9
SDATA  
10  
SCLOCK  
CONTROL LOGIC  
8
SENABLE  
[BOTTOM PLATE]  
C
3
5
12  
14  
FIGURE 1. ISL59920, ISL59921, ISL59922, ISL59923 BLOCK DIAGRAM  
FN6826 Rev 4.00  
August 27, 2015  
Page 1 of 18  

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