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ISL45042IRZ-TK PDF预览

ISL45042IRZ-TK

更新时间： 2024-01-12 01:29:19
品牌 Logo 应用领域
英特矽尔 - INTERSIL 商用集成电路光电二极管
页数 文件大小 规格书
8页 130K
描述
LCD Module Calibrator

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ISL45042IRZ-TK 技术参数

生命周期：Unknown零件包装代码：DFN
包装说明：VSON,针数：8
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：6 weeks风险等级：5.03
其他特性：ALSO REQUIRES 4.5V TO 20V SUPPLY商用集成电路类型：CONSUMER CIRCUIT
JESD-30 代码：S-PDSO-N8JESD-609代码：e3
长度：3 mm湿度敏感等级：2
功能数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：VSON
封装形状：SQUARE封装形式：SMALL OUTLINE, VERY THIN PROFILE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：0.75 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn) - annealed
端子形式：NO LEAD端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：3 mmBase Number Matches：1

ISL45042IRZ-TK 数据手册

 浏览型号ISL45042IRZ-TK的Datasheet PDF文件第2页浏览型号ISL45042IRZ-TK的Datasheet PDF文件第3页浏览型号ISL45042IRZ-TK的Datasheet PDF文件第4页浏览型号ISL45042IRZ-TK的Datasheet PDF文件第5页浏览型号ISL45042IRZ-TK的Datasheet PDF文件第7页浏览型号ISL45042IRZ-TK的Datasheet PDF文件第8页 
ISL45042  
Table 1 gives the calculated value of VOUT for resistors  
values of: R = 24.9kΩ, R1 = 200kΩ, R2 = 243kΩ, and  
Generating VDD and CE supply from a Larger  
Voltage Source  
SET  
= 10V.  
V
ADD  
The CE pin has an internal pull-down resistor (R  
INTERNAL  
TABLE 1. CALCULATED VCOM OUTPUT VOLTAGES  
Figure 5). The impedance of this resistor is 400kΩ-500kΩ. If  
your design is using a resistor divider network to generate  
SETTING VALUE  
VOUT  
5.468  
5.313  
5.141  
4.969  
4.797  
4.625  
4.453  
4.281  
4.109  
3.936  
3.764  
3.592  
3.282  
the 3.3V supply (for both V  
and CE to enable  
DD  
1
programming) from a larger voltage source, the 400kΩ  
(worst case) resistor needs to be taken into account as a  
parallel resistance when the CE pin is connected to this  
source. Another design concern is to be able to provide  
enough supply current during programming. The ISL45042  
draws about 2mA during this process. Recommended  
resistor values are shown in Figure 5. This design will result  
in an additional 0.83mA quiescent current flowing through  
10  
20  
30  
40  
50  
60  
resistors R and R ..  
A
B
70  
VCC= 5V  
80  
ISL45042  
R
90  
A
2kΩ  
100  
110  
128  
CE LOGIC  
CE  
VCE  
R
B
R
Resistor  
SET  
4kΩ  
R
= 400kΩ to 500kΩ  
INTERNAL  
The external R  
resistor sets the full-scale sink current  
SET  
that determines the lowest voltage of the external voltage  
divider R and R (Figure 1). The maximum I current has  
1
2
SET  
resistor with  
to be less than 120μA. The minimum R  
SET  
FIGURE 5. APPLICATION GENERATING VDD AND VCE  
VOLTAGES  
A
equal to 10V is 4.17kΩ (10V/(20*120μA). Typical  
VDD  
applications with A  
equal to 10V and R  
equal to  
VDD  
SET  
24.9kΩ will result in a set current equal to 20μA.  
ISL45042 Truth Table  
Power Supply Sequence  
The ISL45042 truth table is shown in Table 2. For proper  
operation the CE should be disabled (pulled low) before  
powering the device down to assure that the glitches and  
transients will not cause unwanted EEPROM overwriting.  
The recommendation for power supply sequence would be  
to power down the part first (Vdd, AVdd), after 100msec if  
programming has occurred, and then power down the  
control power supplies (CTL, CE).  
TABLE 2. TRUTH TABLE  
Verifying the Programmed Value  
INPUT  
CE  
Hi  
OUTPUT  
ICC  
The following sequence can be used to verify the  
programmed value without having to sequence the V  
supply. To verify the programmed value, follow the steps  
below. The ISL45042 will read memory contents and be set  
to that value when the CE pin is grounded.  
CTL  
Mid to Hi  
Mid to Lo  
X
VDD  
VDD  
VDD  
VDD  
VDD  
OUT  
MEMORY  
DD  
Increment  
Decrement  
Normal  
Normal  
X
X
Hi  
Lo  
No Change Increased  
Read  
1. Power up the ISL45042.  
2. CE pin = V  
DD.  
>4.9V  
Hi  
No Change Increased Program  
3. Change counter value with CTL pin to desired value.  
4. CTL = more than 4.9V and 200msec. Counter value  
programmed.  
5. Change the counter value with CTL pin to a different  
value.  
6. CE pin = Ground.  
7. Check that the output value is the one programmed in  
step #4.  
FN6072.6  
November 14, 2006  
6
1...345678

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