ISL29125
the actual count stored in Registers 0x9 and 0xA for Green or
Registers 0xB and 0xC for Red or Register 0xD and 0xE for Blue
are outside the user’s programmed window. Once ISL29125
issues the interrupt flag, the interrupt status (RGBTHF) bit at
Reg0x08 is asserted to logic HIGH and the INT pin goes low. Both
the INT pin and the interrupt status bit are automatically cleared at
the end of the 8-bit Device Register byte (0x08) transfer. By default
(RGBTHF) bit is LOW or it is within the interrupt thresholds window.
Principles of Operation
Photodiodes and ADC
The ISL29125 contains three photodiode arrays, which convert
light into current. The spectral response for RED, GREEN and
BLUE color ambient intensity sensing is shown in Figure 2. After
light is converted to current during the light to signal process, the
current output is converted to a digital count by an on-chip
Analog-to-Digital Converter (ADC). The ADC converter resolution
is selectable from 12 or 16 bits. The ADC conversion time is
inversely proportional to the ADC resolution.
Power-On Reset
The Power-On Reset (POR) circuitry protects the internal logic
against powering up in the incorrect state. The ISL29125 will
power up into Standby mode after VDD exceeds the POR trigger
level and will power down into Reset mode when VDD drops
below the POR trigger level. This bidirectional POR feature
protects the device against ‘brown-out’ failure following a
temporary loss of power.
The ADC converter uses an integrating architecture. This
conversion method is ideal for converting small signals in the
presence of a periodic noise. A 100ms integration time (16-bit
mode) for instance, rejects 50Hz and 60Hz power line as well as
florescent flicker noise.
The ADC integration time is determined by an internal oscillator
and the n-bit (n = 12, 16) counter inside the ADC. A good
balancing act of integration time and resolution depends on the
application for optimum system performance.
The POR is an important feature because it prevents the
ISL29125 from starting to operate with insufficient power supply
voltage. The ISL29125 prevents communication to its registers
and reduces the likelihood of data corruption on power-up.
The ADC provides two programmable ranges to dynamically
accommodate different lighting conditions. For dim conditions,
the ADC can be configured at its high sensitivity (low optical)
range. For bright conditions, the ADC can be configured at its low
sensitivity (higher optical) range. Note that the effective optical
sensitivity of the ISL29125 in terms of counts/µW/cm2 is
directly proportional to the ADC integration time.
Serial Interface
The ISL29125 supports the Inter-Integrated Circuit (I2C) bus data
transmission protocol. The I2C bus is a two-wire serial
bidirectional interface consisting of SCL (clock) and SDA (data).
Both the wires are connected to the device supply via pull-up
resistors. The I2C protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and the
device being controlled is the slave. The transmitting device pulls
down the SDA line to transmit a “0” and releases it to transmit a
“1”. The master always initiates the data transfer, only when the
bus is not busy and provides the clock for both transmit and
receive operations. The ISL29125 operates as a slave device in
all applications. The serial communication over the I2C interface
is conducted by sending the Most Significant Bit (MSB) of each
byte of data first.
SYNC Mode
SYNC mode is when B5 at Reg0x1 is set to ‘1’, the INT pin
becomes an input pin. This mode is beneficial for some systems
which have multiple sensors on I2C bus. Once B5 is set, on the
rising edge of INT the ADC starts conversion so that multiple
devices would measure at exactly the same time. Yet, to read
data out, the system needs to have a different I2C address for
each sensor or have a multiplexer. Moreover, if B5 is set to ‘0’,
then INT pin will be asserted whenever the sensor triggers an
interrupt.
Start Condition
Interrupt Function
During data transfer, the SDA line must remain stable while the
SCL line is HIGH. All I2C interface operations must begin with a
START condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH (refer to Figure 9). The ISL29125 continuously
monitors the SDA and SCL lines for the START condition and does
not respond to any command until this condition is met (refer to
Figure 9). A START condition is ignored during the power-up
sequence.
The active low interrupt pin is an open-drain pull-down
configuration. The interrupt pin serves as an alarm or monitoring
function to determine whether the ambient light level exceeds
the upper threshold or goes below the lower threshold. It should
be noted that the function of ADC conversion continues without
stopping after interrupt is asserted. If the user needs to read the
ADC count that triggers the interrupt, the reading should be done
before the data registers are refreshed by the following
conversions. The user can also configure the persistency of the
interrupt pin. This reduces the possibility of false triggers, such as
noise or sudden spikes in ambient light conditions. An
unexpected camera flash, for example, can be ignored by setting
the persistency to 8 integration cycles. ISL29125 interrupt
modes can be selected at Bit[1:0] at Reg0x03 Table 11. The user
can select Red, Green or Blue to be the interrupt target. An
interrupt event (RGBTHF) bit at Reg0x08 is governed by Registers
4 through 7. The user writes a high and low threshold value to
these registers and the ISL29125 will issue an interrupt flag if
Stop Condition
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL is
HIGH (refer to Figure 9). A STOP condition at the end of a
read/write operation places the device in its standby mode. If a
stop is issued in the middle of a Data byte, or before 1 full Data
byte and ACK is sent, then the serial communication of ISL29125
resets itself without performing the read/write. The contents of
the register array are not affected.
FN8424 Rev.3.00
Jan 13, 2017
Page 6 of 17
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