ISL29125
2
I C Interface Specifications VDD = 3.0V, TA = +25°C, 16-bit ADC operation, unless otherwise specified.
MIN
MAX
SYMBOL
VIL
PARAMETER
CONDITIONS
(Note 6)
1.25
0
TYP
(Note 6) UNIT
SDA and SCL Input Buffer LOW Voltage
SDA and SCL Input Buffer HIGH Voltage
0.55
V
V
V
V
VIH
V
Hys (Note 8) SDA and SCL Input Buffer Hysteresis
0.05xVDD
V
OL (Note 8) SDA Output Buffer LOW Voltage
0.4
10
(Open-Drain), Sinking 4mA
C
PIN (Note 8) SDA and SCL Pin Capacitance
TA = +25°C, f = 1MHz, VDD = 5V, VIN = 0V,
pF
VOUT = 0V
fSCL
tIN
SCL Frequency
500
50
kHz
ns
Pulse Width Suppression Time at SDA and SCL Any pulse narrower than the maximum
Inputs
specification is suppressed
tAA
SCL Falling Edge to SDA Output Data Valid
900
ns
ns
tBUF
Time the Bus Must be Free Before the Start of
a New Transmission
1300
tLOW
tHIGH
SCL LOW Time
1300
600
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
kΩ
SCL HIGH Time
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
START Condition Set-Up Time
START Condition Hold Time
Input Data Set-Up Time
Input Data Hold Time
STOP Condition Set-Up Time
600
600
100
30
600
tHD:STHD:ST STOP Condition Hold Time
tHD:ST Output Data Hold Time
600
0
t
t
HD:ST (Note 8) SDA and SCL Rise Time
HD:ST (Note 8) SDA and SCL Fall Time
Cb (Note 8) Capacitive Loading of SDA or SCL
20+0.1xCb
20+0.1xCb
Total on-chip and off-chip
400
R
PU (Note 8) SDA and SCL Bus Pull-Up Resistor Off-Chip
Maximum is determined by tR and tF
1
For Cb = 400pF, maximum is about 2kΩ~ 2.5kΩ
For Cb = 40pF, maximum is about 15kΩ~ 20kΩ
NOTES:
8. Limits should be considered typical and are not production tested.
9. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.
10. Cb is the capacitance of the bus in pF.
FN8424 Rev.3.00
Jan 13, 2017
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