ISD4004 Series
SERIAL PERIPHERAL INTERFACE (SPI) DESCRIPTION
The ISD4004 se rie s ope ra te s from a n SPI se ria l inter-
fa ce. The SPI interfa ce opera tes with the following
protoc ol.
re a d inte rrupt da ta a nd sta rt a ne w ope ra -
tion within the sa me SPI c yc le .
8. An ope ra tion be gins with the RUN bit se t
The da ta tra nsfe r protoc ol a ssum e s tha t the m i-
c roc ontrolle r’s SPI shift re giste rs a re c loc ke d on the
fa lling e dge of the SCLK. With the ISD4004, da ta is
c loc ke d in on the MOSI pin on the rising c loc k
e dge . Da ta is c loc ke d out on the MISO pin on the
fa lling c loc k e dge .
a nd e nds with the RUN bit re se t.
9. All ope ra tions be gin with the rising e dge
of SS.
MESSAGE CUEING
1. All se ria l da ta tra nsfe rs be gin with the fa lling
Me ssa ge c ue ing a llows the use r to skip through
m e ssa ge s, without knowing the a c tua l physic a l lo-
c a tion of the m e ssa ge . This ope ra tion is use d dur-
ing pla yba c k. In this m ode , the m e ssa ge s a re
skippe d 1600 tim e s fa ste r tha n in norm a l pla y-
ba c k m ode . It will stop whe n a n EOM m a rke r is
re a c he d. The n, the inte rna l a ddre ss c ounte r will
point to the ne xt m e ssa ge .
e dge of SS pin.
2. SS is held LOW during a ll seria l c ommunica -
tions a nd he ld HIGH be twe e n instruc tions.
3. Da ta is c loc ke d in on the rising c loc k e dge
a nd da ta is c loc ke d out on the fa lling c loc k
e dge .
4. Pla y a nd Re c ord ope ra tions a re initia te d by
e na bling the de vic e by a sse rting the SS pin
LOW, shifting in a n opc ode a nd a n a ddre ss
fie ld to the ISD4004 de vic e (re fe r to the Op-
c ode Sum m a ry on the pa ge 6).
5. The opc ode s a nd a ddre ss fie lds a re a s fol-
lows: < 8 c ontrol bits> a nd < 16 a ddre ss
bits> .
6. Ea c h ope ra tion tha t e nds in a n EOM or
Ove rflow will ge ne ra te a n inte rrupt, inc lud-
ing the Me ssa ge Cue ing c yc le s. The Inte r-
rupt will be c le a re d the ne xt tim e a n SPI
c yc le is initia te d.
7. As Inte rrupt da ta is shifte d out of the
ISD4004 MISO pin, c ontrol a nd a ddre ss
da ta is sim ulta ne ously be ing shifte d into
the MOSI pin. Ca re should be ta ke n suc h
tha t the da ta shifte d in is c om pa tible with
c urre nt syste m ope ra tion. It is possible to
ISD
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