ISD4004 Series
NON-INVERTING ANALOG INPUT (ANA IN+)
SLAVE SELECT (SS)
This pin is the non-inve rting a na log input tha t tra ns-
fe rs the signa l to the de vic e for re c ording. The a n-
a log input a m plifie r c a n be drive n single e nde d or
diffe re ntia lly. In the single -e nde d input mode, a
32 mVp-p (pea k-to-pe a k) ma ximum signa l should
be c a pa c itive ly c onne c te d to this pin for optim a l
signa l qua lity. This c a pa c itor va lue , toge the r with
the 3 KW input im pe da nc e of ANA IN+ , is se le c te d
to give c utoff a t the low fre que nc y e nd of the
voic e pa ssba nd. In the diffe re ntia l-input m ode ,
the m a xim um input signa l a t ANA IN+ should be
16 m Vp-p for optima l signa l qua lity. The c irc uit
c onne c tions for the two m ode s a re shown in Fig-
ure 2 on pa ge 2.
This input, whe n LOW, will se le c t the ISD4004
de vic e .
MASTER OUT SLAVE IN (MOSI)
This is the se ria l input to the ISD4004 de vic e . The
m a ste r m ic roc ontrolle r pla c e s da ta on the MOSI
line one ha lf-c yc le be fore the rising c loc k e dge to
be c loc ke d in by the ISD4004 de vic e .
MASTER IN SLAVE OUT (MISO)
This is the se ria l output of the ISD4004 de vic e . This
output goe s into a high-im pe da nc e sta te if the
de vic e is not se le c te d.
SERIAL CLOCK (SCLK)
INVERTING ANALOG INPUT (ANA IN–)
This is the c loc k input to the ISD4004. It is ge ne ra t-
e d by the m a ste r de vic e (mic roc ontrolle r) a nd is
use d to sync hronize da ta tra nsfe rs in a nd out of
the de vic e through the MISO a nd MOSI line s. Da ta
is la tc he d into the ISD4004 on the rising e dge of
SCLK a nd shifte d out of the de vic e on the fa lling
e dge of SCLK.
This pin is the inve rting a na log input tha t tra nsfe rs
the signa l to the de vic e for re c ording in the diffe r-
e ntia l-input m ode . In this diffe re ntia l-input m ode ,
a 16 m Vp-p m a xim um input signa l a t ANA IN–
should be c a pa c itive ly c ouple d to this pin for op-
tim a l signa l qua lity a s shown in the ISD4004 Se rie s
ANA IN Mode s, Figure 2. This c a pa c itor va lue
should be e qua l to the c oupling c a pa c itor use d
on the ANA IN+ pin. The input impeda nce a t ANA IN–
is nomina lly 56 KW. In the single -e nde d m ode , ANA
INTERRUPT (INT)
The ISD4004 inte rrupt pin goe s LOW a nd sta ys LOW
whe n a n Ove rflow (OVF) or End of Me ssa ge (EOM)
m a rke r is de te c te d. This is a n ope n dra in output
pin. Ea c h ope ra tion tha t e nds in a n EOM or Ove r-
flow will ge ne ra te a n inte rrupt inc luding the m e s-
sa ge c ue ing c yc le s. The inte rrupt will be c le a re d
the ne xt tim e a n SPI c yc le is initia te d. The inte rrupt
sta tus c a n be re a d by a n RINT instruc tion.
IN– should be c a pa c itive ly c ouple d to V
SSA
through a c a pa c itor e qua l to tha t use d on the
ANA IN+ input.
AUDIO OUTPUT (AUD OUT)
This pin provide s the a udio output to the use r.
It is c a pa ble of driving a 5 KW im pe da nc e . It is
re c om m e nde d tha t this pin be AC c ouple d.
Ove rflow Fla g (OVF)—The Ove rflow fla g indi-
c a te s tha t the e nd of the ISD4004’s a na log m e m -
ory ha s be e n re a c he d during a re c ord or
pla yba c k ope ra tion.
NOTE The AUDOUT p in is a lwa ys a t 1.2 volts whe n
the de vice is p owe re d up . Whe n in p la y-
ba c k, the outp ut buffe r c onne c te d to this
p in ca n drive a loa d a s sm a ll a s 5 KW.
Whe n in re cord, a re sistor c onne c ts AUD-
OUT to the inte rna l 1.2 volt a na log g round
sup p ly. This re sistor is a p p roxim a te ly
850 KW, but will va ry som e wha t a c cording
to the sa m p le ra te of the de vice . This re l-
a tive ly hig h im p e da nc e a llows this p in to
be c onne c te d to a n a udio bus without
loa ding it down.
End of Me ssa g e (EOM)—The End-of-Me ssa ge
fla g is se t only during pla yba c k ope ra tion whe n a n
EOM is found. The re a re e ight EOM fla g position
options pe r row.
ISD
3
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