®
IS93C46A
IS93C56A
IS93C66A
ISSI
Write Enable (WEN)
Write All (WRALL)
The write enable (WEN) instruction must be executed
before any device programming (WRITE, WRALL,
ERASE, and ERAL) can be done. When Vcc is applied,
this device powers up in the write disabled state. The
devicethenremainsinawritedisabledstateuntilaWEN
instruction is executed. Thereafter, the device remains
enabled until a WDS instruction is executed or until Vcc
is removed. (See Figure 4.) (Note: Chip select must
remain LOW until Vcc reaches its operational value.)
Thewriteall(WRALL)instructionprogramsallregisterswith
the data pattern specified in the instruction.
As with the WRITE instruction, the falling edge of CS must
occur to initiate the self-timed programming cycle. If CS is
thenbroughtHIGHafteraminimumwaitof250ns(tCS),the
DOUT pinindicatestheREADY/BUSYstatusofthechip(see
Figure6).
Write Disable (WDS)
The write disable (WDS) instruction disables all programming
capabilities. This protects the entire device against acci-
dental modification of data until a WEN instruction is
executed. (When Vcc is applied, this part powers up in the
write disabled state.) To protect data, a WDS instruction
should be executed upon completion of each programming
operation.
Write (WRITE)
TheWRITEinstructionincludes8or16bitsofdatatobe
written into the specified register. After the last data bit
has been applied to DIN, and before the next rising edge
of SK, CS must be brought LOW. The falling edge of CS
initiates the self-timed programming cycle.
After a minimum wait of 250 ns (5V operation) from the
falling edge of CS (tCS), if CS is brought HIGH, DOUT will
indicate the READY/BUSY status of the chip: logical “0”
meansprogrammingisstillinprogress;logical“1”means
the selected register has been written, and the part is
readyforanotherinstruction(seeFigure5).(NOTE:The
combination of CS HIGH, DIN HIGH and the rising edge
of the SK clock, resets the READY/BUSY flag. There-
fore, toaccesstheREADY/BUSYflag,thiscombination
of control signals should be avoided.) Before a WRITE
instruction can be executed, the device must be write
enabled(seeWEN).
Erase Register (ERASE)
After the erase instruction is entered, CS must be brought
LOW.ThefallingedgeofCSinitiatestheself-timedinternal
programming cycle. Bringing CS HIGH after a minimum of
tCS, will cause DOUT to indicate the READ/BUSY status of the
chip:alogical“0”indicatesprogrammingisstillinprogress;
a logical “1” indicates the erase cycle is complete and the
part is ready for another instruction (see Figure 8).
Erase All (ERAL)
Fullchiperaseisprovidedforeaseofprogramming.Erasing
the entire chip involves setting all bits in the entire memory
array to a logical “1” (see Figure 9).
INSTRUCTION SET - IS93C46A
8-bitOrganization
16-bitOrganization
(ORG = GND)
(ORG = Vcc)
(1)
(1)
Instruction
READ
Start Bit
OP Code
10
Address
Input Data
Address
Input Data
1
1
1
(A6-A0)
11xxxxx
(A6-A0)
01xxxxx
00xxxxx
(A6-A0)
10xxxxx
—
—
(A5-A0)
11xxxx
(A5-A0)
01xxxx
00xxxx
(A5-A0)
10xxxx
—
—
WEN (Write Enable)
WRITE
00
(3)
(2)
01
(D7-D0)
(D15-D0)
(3)
(2)
WRALL (Write All Registers)
WDS (Write Disable)
ERASE
1
1
1
1
00
(D7-D0)
(D15-D0)
00
—
—
—
—
—
—
11
ERAL (Erase All Registers)
00
Notes:
1. x = Don't care bit.
2. If input data is not 16 bits exactly, the last 16 bits will be taken as input data.
3. If input data is not 8 bits exactly, the last 8 bits will be taken as input data.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00APRELIMINARYINFORMATION
3
05/07/02
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