Datasheet > 暂无类别数据> IS61QDPB44M18-333M3L

IS61QDPB44M18-333M3L

更新时间： 2024-09-29 05:39:35

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
28页	669K
描述
72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs

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72 Mb (2M x 36 & 4M x 18)

QUADP (Burst of 4) Synchronous SRAMs

May 2009

Features

• 2M x 36 or 4M x 18.

• +1.8V core power supply and 1.5, 1.8V V_DDQ

used with 0.75, 0.9V V_REF

• On-chip delay-locked loop (DLL) for wide data

valid window.

• HSTL input and output levels.

• Separate read and write ports with concurrent

read and write operations.

• Registered addresses, write and read controls,

byte writes, data in, and data outputs.

• Synchronous pipeline read with late write opera-

tion.

• Full data coherency.

• Boundary scan using limited set of JTAG 1149.1

functions.

• Double data rate (DDR) interface for read and

write input ports.

• Byte write capability.

• Fixed 4-bit burst for read and write operations.

• Clock stop support.

• Fine ball grid array (FBGA) package

- 15mm x 17mm body size

- 1mm pitch

• Two input clocks (K and K) for address and con-

trol registering at rising edges only.

- 165-ball (11 x 15) array

• Two echo clocks (CQ and CQ) that are delivered

• Programmable impedance output drivers via 5x

user-supplied precision resistor.

simultaneously with data.

Description

The 72Mb IS61QDPB42M36 and

• Byte writes for burst addresses 2 and 4

• Data-in for burst addresses 2 and 4

IS61QDPB44M18 are synchronous, high-perfor-

mance CMOS static random access memory

(SRAM) devices. These SRAMs have separate I/Os,

eliminating the need for high-speed bus turnaround.

The rising edge of K clock initiates the read/write

operation, and all internal operations are self-timed.

Refer to the Timing Reference Diagram for Truth

Table on page 8 for a description of the basic opera-

tions of these QUADP (Burst of 4) SRAMs.

Byte writes can change with the corresponding data-

in to enable or disable writes on a per-byte basis. An

internal write buffer enables the data-ins to be regis-

tered one cycle after the write address. The first

data-in burst is clocked one cycle later than the write

command signal, and the second burst is timed to

the following rising edge of the K clock. Two full

clock cycles are required to complete a write opera-

tion.

Read and write addresses are registered on alter-

nating rising edges of the K clock. Reads and writes

are performed in double data rate. The following are

registered internally on the rising edge of the K

clock:

The device is operated with a single +1.8V power

supply and is compatible with HSTL I/O interfaces.

• Read/write address

• Read enable

• Write enable

• Byte writes for burst addresses 1 and 3

• Data-in for burst addresses 1 and 3

The following are registered on the rising edge of

the K clock:

Integrated Silicon Solution, Inc.

Rev. A

05/14/09

12 3 4 5 6 7...28

中文翻译

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与IS61QDPB44M18-333M3L相关器件

型号	品牌	获取价格	描述	数据表
IS61QDPB44M18-375M3	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs
IS61QDPB44M18-375M3L	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs
IS61QDPB44M18-400M3	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs
IS61QDPB44M18-400M3L	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs
IS61QDPB44M18A	ISSI	获取价格	2Mx36 and 4Mx18 configuration available
IS61QDPB44M18A1	ISSI	获取价格	2Mx36 and 4Mx18 configuration available
IS61QDPB44M18A2	ISSI	获取价格	2Mx36 and 4Mx18 configuration available
IS61QDPB44M18B	ISSI	获取价格	2Mx36 and 4Mx18 configuration available
IS61QDPB44M18B1	ISSI	获取价格	2Mx36 and 4Mx18 configuration available
IS61QDPB44M18B2	ISSI	获取价格	2Mx36 and 4Mx18 configuration available

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